Method for fabricating a transistor using a SOI wafer

Details Method for fabricating a transistor using a SOI wafer Method for fabricating a transistor using a SOI wafer

2006-12-22

2009-11-24

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S283000, C438S595000, C257SE21561

Reexamination Certificate

active

07622337

ABSTRACT:
Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.

REFERENCES:
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6930359 (2005-08-01), Ushiku
patent: 7005302 (2006-02-01), Xiang
patent: 7205185 (2007-04-01), Dokumaci et al.
patent: 7247910 (2007-07-01), Lee et al.
patent: 7265031 (2007-09-01), Oh et al.
patent: 7265424 (2007-09-01), Hofmann et al.
patent: 2004/0209438 (2004-10-01), Saito et al.
patent: 2005/0067659 (2005-03-01), Gutsche et al.
patent: 2006/0138542 (2006-06-01), Xiang
patent: 2008/0035997 (2008-02-01), Hofmann et al.
Ginsberg, B.J., “Selective epitaxial growth of silicon and some potential applications”, IBM Journal of Research and Development, Vol. 34, No. 6, p. 816, Nov. 1990.
Wong, S.S. et al “Elevated source/drain Mosfet”, Dec. 1984, IEDM Tech. Dig., p. 634.

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