Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-08-21
2007-08-21
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S029000, C438S736000, C438S738000
Reexamination Certificate
active
10795787
ABSTRACT:
A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.
REFERENCES:
patent: 6468840 (2002-10-01), Tanaka et al.
patent: 6902852 (2005-06-01), Watanabe
patent: 2002/0085161 (2002-07-01), Yoo et al.
patent: 2000012541 (2000-01-01), None
patent: 2001-311965 (2001-11-01), None
patent: 02002184999 (2002-06-01), None
Duong Khanh
Greer Burns & Crain Ltd
Wilczewski M.
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