Method for fabricating a thin-film transistor

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437101, 437913, 437937, H01L 2186

Patent

active

054707684

ABSTRACT:
To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower. For a stagger-type thin-film transistor, the hydrogen or halogen content of an insulating film serving as the substrate of source and drain electrodes is increased. For an inverted-stagger thin-film transistor, the hydrogen or halogen content of an insulating film serving as a channel protective film is increased. Thus, the etching rate of the surfaces of these insulating films by plasma increases.

REFERENCES:
patent: 4477311 (1984-10-01), Mimura et al.
patent: 4579609 (1986-04-01), Reif et al.
patent: 4800174 (1989-01-01), Ishihara et al.
patent: 4842897 (1989-06-01), Takeuchi et al.
patent: 4849375 (1989-07-01), Gluck et al.
patent: 4880753 (1989-11-01), Meakin et al.
patent: 5194398 (1993-03-01), Miyachi et al.
patent: 5221643 (1993-06-01), Griep
patent: 5238866 (1993-08-01), Bolz et al.
patent: 5242530 (1993-09-01), Batey et al.
patent: 5288658 (1994-02-01), Ishihara
Selective Deposition and Bond Strain Relaxation in Silicon PECVD Using Time Modulated Silane Flow, G. N. Parsons et al., Japanese Journal of Applied Physics, Part 1 Jun. 1992, pp. 1943-1947, vol. 31 No. 6B.
Selective Tungsten on Silicon by the Alternating Cyclic, AC, Hydrogen reduction of WF/sub 6/', A. Reisman et al., Journal of the Electrochemical Society, Feb. 1990, USA, vol. 137, No. 2, pp. 722-727.
"Enhanced Mobility Top-Gate Amorphous Silicon Thin-Film Transistor with Selectively Deposited Source/Drain Contacts," G. N. Parsons, IEEE Electron Devices Letters, vol. 2, Feb. 1992, pp. 80-82.
"Selective Deposition of Silicon by Plasma-Enhanced Chemical Vapor Deposition Using Pulsed Silane Flow," G. N. Parsons, Appl. Phys. Lett. 59 (20), Nov. 1991, pp. 2546-2548.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating a thin-film transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a thin-film transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a thin-film transistor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2013087

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.