Method for fabricating a silicon-on-insulator voltage multiplier

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257350, 257352, H01L 2900

Patent

active

H00014230

ABSTRACT:
The present invention provides a method for fabricating a silicon-on-insulator voltage multiplier. The method comprises the steps of: forming a first silicon layer having a first concentration of a first dopant with a first polarity on a silicon wafer having a second concentration of a second dopant with a second polarity opposite the first polarity to create a diode junction; forming a second silicon layer on the first silicon layer, the second silicon layer having a third concentration of a third dopant having the first polarity, where the third concentration is greater than the first concentration of the first dopant; forming a silicon dioxide layer on the second silicon layer by thermal oxidation; bonding an insulating substrate to the silicon dioxide layer to create a bonded wafer, where the insulating substrate is selected from the group consisting of quartz, glass, sapphire, and silicon dioxide on silicon; thinning the silicon wafer to form a thinned silicon layer; etching the bonded wafer to form a plurality of separate diodes having sloped sidewalls and to expose selected regions of the insulating substrate; forming an insulating silicon layer on the selected regions of the insulating substrate and on the separate diodes; exposing selected regions of the thinned silicon layer and regions of the second silicon layer of each of the diodes; and forming metal interconnects between the exposed selected regions of the thinned silicon layer of one of the diodes with the silicon layer of another of the diodes.

REFERENCES:
patent: 4241360 (1980-12-01), Hambor et al.
patent: 4501060 (1985-02-01), Frye et al.
patent: 4520461 (1985-05-01), Simko
patent: 4575746 (1986-03-01), Dingwall
patent: 4922403 (1990-05-01), Feller
patent: 5014097 (1991-05-01), Kazerounian
"Method to Form Very Thin SOI Films", IBM Technical Disclosure Bulletin, . 35, #2 Jul. 1992, pp. 37-38.
"Process for Fabrication of Very Thin Epitaxial Silicon Films Over Insulating Layers," IBM Technical Disclosure Bulletin, vol. 35, #2, Jul. 1992, pp. 247-249.

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