Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-21
2001-09-11
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S423000, C438S524000, C438S530000
Reexamination Certificate
active
06287939
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of semiconductor devices and more particularly to fabrication of a shallow trench isolation which is not susceptable to buried contact trench formation.
2. Description of the Prior Art
As device dimensions and die sizes continue to decrease to aceive higher density integrated circuits, there is a growing demand for more effective isolation technology. Shallow trench isolation (STI) technology has become more widely used due to the lack of encroachment like the “bird beak” in LOCOS technology and due to the lower susceptability to “Latch-up.” However, several problems exist with conventional shallow trench isolation technology. If misalignment occurs during the contact etching process, a trench can form in the buried contact. This trench, known as a buried contact trench creates a leakage path between the contact and the substrate.
Another problem associated with shallow trench isolation technology is called the “kink effect” caused by oxide thinning. During conventional STI etch, a recess is formed near the edge of the STI. This geometry causes the gate oxide to be thinner over the edge formed where the recess begins, resulting in a reduced threshhold voltage and additional standby current.
Recent research has shown several advantages to nitrogen implantation into silicon dioxide isolations. For example, Formation of Ultrathin Nitrided SiO2 Oxides by direct Nitrogen Implantation into Silicon, Journal of Electrochemical Society, Vol. 142 No. 8, August 1995, discloses a process for silicon dioxide nitridation to improve resistance to the hot carrier effect while minimizing ion implantation damage. Another article, High Performance 0.2 &mgr;m CMOS with 25 Å Gate Oxide Grown on Nitrogen Implanted Si Substrates, IEDM 96-499, discloses that implanted nitrogen can prevent Boron penetration and supress short-channel effect and drain induced barrier lowering (DIBL) effect.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,316,965 (Philipossian et al.) shows a nitrogen ion implantation to acheive a comparable etch rate to a thermal oxide pad layer.
U.S. Pat. No. 5,468,657 (Hsu) discloses a SIMOX process with N
2
ion implant into the oxide.
U.S. Pat. No. 5,516,707 (Loh et al.) shows an angled nitrogen implantation into source/drain regions to improve hot carrier immunity.
U.S. Pat. No. 5,741,740 (Jang et al.) shows a method of filling a trench which may include nitrogen treatment of a liner oxide prior to filling the trench.
U.S. Pat. No. 5,763,315 (Benedict et al.) shows an oxynitride liner formation prior to filling a trench.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation.
It is another object of the present invention to provide a method for fabricating a shallow trench isolation with immunity from the “Kink effect.”
It is another object of the present invention to provide a method for fabricating a shallow trench isolation wherein nitridation prevents boron penetration.
It is yet another object of the present invention to provide a method for fabricating a shallow trench isolation wherein nitridation reduces short channel effect and DIBL effect.
To accomplish the above objectives, the present invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The process begins by forming a pad oxide layer (
12
) on a semiconductor substrate (
10
). A nitride layer (
14
) is formed on the pad oxide layer (
12
). The nitride layer (
14
), the pad oxide layer (
12
), and the semiconductor substrate (
10
) are patterned to form trenches (
16
). Next, a fill oxide layer (
18
) is formed over the nitride layer (
14
), the pad oxide layer (
12
), and the semiconductor substrate (
10
). The fill oxide layer (
18
) is chemical-mechanical polished, stopping on the nitride layer (
14
) to form fill oxide regions (
18
A). N
2
ions are implanted into the fill oxide regions (
18
A). An anneal is performed to form a buried oxynitride layer (
20
). The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate (
10
) and partially below the level of the top surface of the semiconductor substrate (
10
). The nitride layer (
14
) is removed. Then, the pad oxide layer (
12
) and portions of the fill oxide regions (
18
A) are removed using the buried oxynitride layer (
20
) as an etch stop, forming shallow trench isolations (
22
).
The present invention provides considerable improvement over the prior art. In the present invention a buried oxynitride layer is formed beneath the surface of the fill oxide formed in isolation trenches. This oxynitride layer can be used as an etch stop during etching of the overlying fill oxide and the pad oxide preventing recesses and the kink effect. When the buried oxynitride layer is formed at a depth where a portion is below the level of the adjacent substrate, that portion is left to prevent trenching during contact overetch. The nitridation also provides additional benefits known in the art.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4968636 (1990-11-01), Sugawara
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5468657 (1995-11-01), Hsa
patent: 5516707 (1996-05-01), Loh et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5902127 (1999-05-01), Park
patent: 5923993 (1999-07-01), Sahota
patent: 6211021 (2001-04-01), Wang et al.
Soleimani et al. “Formation of Ultrathin Nitrided SiO2Oxides by Direct Nitrogen Implantation into Silicon”, Journal of Electrochemical Society, vol. 142, No. 8, Aug. 1995, p132-134.
“High Performance 0.2 &mgr;m CMOS with 25 ↑ Gate oxide Grown on Nitrogen Implanted SiSubstrates” IEDM 96-499-502.
Chiang Wen-Chuan
Huang Kuo Ching
Ying Tse-Liang
Ackerman Stephen B.
Chaudhuri Olik
Duy Mai Anh
Saile George O.
Stoffel William J.
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