Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1998-12-23
2001-10-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S424000
Reexamination Certificate
active
06303461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a shallow trench isolation (STI) structure with a prevention of dishing phenomenon.
2. Description of Related Art
An isolation structure is used to prevent carriers from drifting between two adjacent devices, such as metal-oxide semiconductor (MOS) transistors, through a semiconductor substrate, on which the MOS transistors are formed. So, a charge leakage occurring on the MOS transistors is also avoided. As device integration continuously increases and line width continuously decreases, the fabrication process has achieved to a fabrication level of 0.25 microns or less. At this fabrication level, using STI structure for the isolation purpose becomes a necessary strategy. A STI structure, typically, is formed by patterning a semiconductor substrate by photolithography and anisotropic etching to form a shallow trench in the substrate, and filling the trench with insulating material.
When fabrication level reaches to about 0.25 microns or less, a chemical mechanical polishing (CMP) process is also widely used to globally planarize or polish the structures formed over the substrate. The STI structure conventionally needs the CMP process to polish undesired insulating material deposited on the substrate. However, the CMP process also causes a dishing issue.
FIG.
1
A and
FIG. 1B
are cross-sectional views of a portion of a substrate, schematically illustrating a conventional fabrication process to form a STI structure. In
FIG. 1A
, a pad oxide layer
12
is formed on a semiconductor substrate
10
. A silicon nitride layer
14
is formed on the pad oxide layer
12
. Patterning the silicon nitride layer
14
, the pad oxide layer
12
, and the substrate
10
forms a trench
15
a
and a trench
15
b
in the substrate
10
, in which the trench
15
b
is wider than the trench
15
a
. An oxide layer
16
is formed over the substrate
10
so that the trenches
15
a
,
15
b
are also filled by oxide. The top surface of the oxide layer
16
is not planar due to a concave structure of the trenches
15
a
,
15
b
. Several silicon-nitride flat regions
14
a
,
14
b
between the trenches
15
a
,
15
b
are also simultaneously formed after patterning. The silicon-nitride flat region
14
b
is wider than the silicon-nitride flat region
14
a
. The oxide layer
16
is formed by chemical vapor deposition (CVD).
In
FIG. 1B
, after a densification process is performed on the oxide layer
16
, a CMP process, using the silicon nitride layer
14
as a stop point, is performed to planarize the oxide layer
16
. A remaining portion of the oxide layer
16
becomes an oxide layer
16
a.
While the CMP process is performed, the structure surface of the substrate
10
is pressed onto a rotating polishing pad to achieve a polishing purpose. Since the oxide layer
16
is not planar, the polishing pad may easily get a deformation at a portion above the wider trench
15
b
. After the CMP process, several issues are very possibly induced.
First, a dishing phenomenon
18
occurs on the oxide layer
16
a
filled in the wider trench
15
b
shown in
FIG. 1A
, Second, there is a residue of the oxide layer
16
a
left on the wider silicon-nitride flat region
14
b
. Third, since the substrate
100
includes the siliconnitride flat regions
14
a
,
14
b
and the trenches
15
a
,
15
b
, all of which have different dimension, it is difficult to obtain a sufficient uniformity of the oxide layer
16
a
after the CMP process.
Conventionally, in order to completely remove the residue of the oxide layer
16
a
on the silicon nitride layer
14
, a strategy of over-polishing on the silicon nitride layer
14
is applied. If there is the residue of the oxide layer on the silicon nitride, it causes a difficulty to remove the silicon nitride layer later. However, even though the residue of the oxide layer
16
a
can be completely removed, the dishing phenomenon of the oxide layer
16
a
is aggravated due to a faster polishing rate of the oxide layer
16
a.
Conventionally, in order to solve the dishing issue, a dummy pattern structure is proposed by a conventional method.
FIG. 2
is a cross-sectional view of a portion of a substrate, schematically illustrating a dummy pattern structure. In
FIG. 2
, the like reference number represents the like object. Also referring to FIG.
1
A and
FIG. 1B
, a dummy pattern structure
20
is formed in the wider trench
15
b
so that the trench
15
b
is divided into two trenches
15
c
. In this manner, the width of the trenches
15
c
has not much difference to the trench
15
a
. Since the width of the trench
15
a
is narrowed into the width of the trenches
15
c
the dishing phenomenon is reduced. The dummy pattern structure
20
can reduce the dishing phenomenon but the difference dimension of the silicon-nitride flat regions
14
a
,
14
b
is still not solved yet. This causes the residue of the oxide layer
16
a
remaining on the silicon-nitride layer
14
can not be uniformly removed.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a STI structure, in which a dishing phenomenon is effectively avoided.
It is another an objective of the present invention to provide a method for fabricating a STI structure, in which a residue of an oxide layer is avoided.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabricating a STI structure is provided. The improved method includes sequentially forming a pad oxide layer, a hard layer, and a polysilicon layer on the substrate, all of which are patterned to form a wider trench and a narrower trench in the substrate to define several active areas. The hard layer usually includes silicon nitride. An insulating layer is formed over the substrate so that the wider trench and the narrower trench are also filled. A CMP process is performed to polish the insulating layer. Since the polysilicon layer has faster polishing rate than that of the insulating layer, a dishing phenomenon is completely avoided. The CMP process is continuously performed until the hard layer is completely exposed. The hard layer and the pad oxide layer are sequentially removed to form the STI structure.
In accordance with the foregoing and other objectives of the present invention, another improved method, including a reverse patterning process, for fabricating a STI structure is provided. The improved method including sequentially forming a pad oxide layer, a hard layer, and a polysilicon layer on the substrate, all of which are patterned to form a wider trench and a narrower trench in the substrate to define several active areas. The hard layer typically includes silicon nitride. An insulating layer is formed over the substrate so that the wider trench and the narrower trench are also filled. A reverse patterning process is performed to pre-remove the insulating layer. The reverse patterning process includes performing an etching process, using the polysilicon layer as a etching stop point, to remove the insulating layer at a portion above the active areas. This manner can reduce the duration time of a CMP process performed subsequently. The CMP process is performed to polish both the insulating layer and the polysilicon layer. Since the polysilicon layer includes a faster polishing rate than that of the insulating layer, a dishing phenomenon is completely avoided. The CMP process is continuously performed until the hard layer is fully exposed. The hard layer and the pad oxide layer are respectively removed to form the STI structure.
REFERENCES:
patent: 5786262 (1998-07-01), Jang et al.
patent: 5811345 (1998-09-01), Yu et al.
patent: 5925575 (1999-07-01), Tao et al.
patent: 5994201 (1999-11-01), Lee
patent: 6043133 (2000-03-01), Jang et al.
patent: 6117748 (2000-09-01), Lou et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, 1986, Lattice Press, pp. 177-178.
Chen Chien-Hung
Chen Hsueh-Chung
Jones Josetta I.
Niebling John F.
United Microelectronics Corp.
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