Method for fabricating a semiconductor memory device having...

Details Method for fabricating a semiconductor memory device having... Method for fabricating a semiconductor memory device having...

2000-11-14

2003-01-21

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S396000, C438S565000, C438S660000, C438S253000

Reexamination Certificate

active

06509263

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method for fabricating a semiconductor memory device with a reduced contact resistance.
2. Description of the Related Art
Generally, DRAM is fabricated by using MOS technology to include a number of memory cells each consisting of one transistor and one capacitor, providing large capacity at low power consumption and low cost. Its storage is accomplished by charging the capacitors with binary high or low values, which is different from a SRAM (Static Random Access Memory) storing information in flip-flops. The DRAM requires refresh cycles for recharging the memory cells since the capacitors are discharged after a certain amount of time. Hence, each memory cell requires a refresh period of between 2 nS to 10 nS. As the scale of integration of semiconductor devices increases, a 1G DRAM is expected to store 1-gigabit of information in one chip, whose unit cell has a size of about 0.3 &mgr;m
2
.
FIGS. 1A
to
1
E are layouts for illustrating a general method for fabricating a semiconductor device, and
FIGS. 2A
to
2
F are cross-sectional views taken along line I-I′ of
FIGS. 1A
to
1
E for illustrating a conventional method for fabricating a semiconductor device.
Referring to
FIG. 1A and 2A
, a semiconductor substrate
1
is divided into active regions
2
and field regions. The field region is provided with the field oxide layer
3
. A plurality of word lines
4
with the cap-insulating layers
5
are laid perpendicular to and over the active regions
2
with a predetermined interval between them. The active regions
2
are selectively implanted with impurity ions of low concentration by using the word lines
4
as a mask, forming LDD impurity regions. In this case, each active region is crossed by two word lines
4
. Both sides of each word line
4
are covered with insulating sidewalls
6
, which serve as the mask to implant impurity ions of high concentration into the active regions to form source/drain regions.
Referring to
FIGS. 1B and 2B
, a first polysilicon layer is deposited over the semiconductor substrate
1
. The first polysilicon layer is patterned by photolithographic process to expose the cap insulating layer
5
and to form a plurality of plugs
7
a
,
7
b
over the active regions
2
between the word lines
4
. The plug
7
b
is extended to the region to form the bit line for two cells to commonly occupy a single contact, as shown in FIG.
1
B. In addition, a first interlayer dielectric (WLD)
8
is heavily deposited over the plugs
7
a
,
7
b
, and flattened.
Referring to
FIGS. 1C and 2C
, after forming a bit line contact hole in the plug
7
b
extended to the bit line, tungsten and cap insulating layers are deposited over the substrate including the bit line contact hole, patterned by photolithographic process to form bit line
9
and cap insulating layer (not shown in the drawing) in the direction perpendicular to the word line
4
. Then, a second insulating interlayer
10
is formed over the substrate including the bit line
9
, and then flattened or planarized.
Subsequently, a photoresist (not shown in the drawing) is deposited over the second insulating interlayer
10
, photographically patterned to form first contact holes
11
by etching the second insulating interlayer
10
, bit lines
9
, and first insulating interlayer
8
, as shown in
FIGS. 1D and 2D
. Then, impurity ions are implanted through the first contact holes
11
into the surface of the first polysilicon layer, as shown in
FIGS. 1E and 2E
. Finally, deposited over the second insulating interlayer
10
including the first contact holes
11
is a second polysilicon layer, selectively patterned to form the storage electrodes
12
held by the second insulating interlayer
10
over the active regions
2
, as shown in FIG.
2
F. In this case, the concentration of the second polysilicon is equal to or greater than 1E21/cm
3
.
However, such conventional method for fabricating a semiconductor device suffers the following problems:
As the size of the device is reduced, the contact resistance of doped polysilicon to doped polysilicon is considerably increased compared to metal to silicon, metal to metal, and metal to doped polysilicon. If the contact resistance is reduced by enhancing the concentration of the polysilicon over 1E21/cm
3
, the subsequent heat treatment results in diffusion of the impurities causing refreshment. Moreover, if the surface concentration of the polysilicon is enhanced by plug ion implantation, an additional process is required which results in the formation of a spontaneous oxide layer on the polysilicon surface due to the process delay. This results in an increase of the contact resistance, such that there is a generation of a RC delay of the semiconductor device, which prevents high speed.
SUMMARY OF THE INVENTION
It is a feature of the present invention to provide a method for fabricating a semiconductor device that reduces the contact resistance by enhancing the surface concentration of the polysilicon without any additional process.
According to an aspect of the present invention, a method for fabricating a semiconductor device in a semiconductor substrate divided into active and field regions, comprises the steps of forming a plurality of word lines each having a cap insulating layer with a predetermined interval between adjacent word lines on the substrate, forming source/drain impurity regions in the active regions adjacent to both sides of each of the word lines, forming insulating sidewalls on both sides of each of the word lines, forming capacitor node plugs and bit line contact plugs on the source/drain impurity regions, forming a plurality of bit lines in the direction perpendicular to the word lines with a predetermined interval between adjacent bit lines by forming bit line contact holes contacting the bit line contact plugs in a first insulating interlayer deposited on the substrate, forming storage electrode contact holes to expose the capacitor node plugs in a second insulating interlayer deposited over the substrate, and subjecting the storage electrode contact holes to heat treatment before implanting impurity ions through the storage electrode contact holes into the active regions to grow the storage electrodes.
According to another aspect of the present invention, a method for fabricating a semiconductor device in a semiconductor substrate divided into active and field regions, the field regions being provided with field oxide layers, comprises the steps of forming a plurality of word lines each having a cap insulating layer with a predetermined interval between adjacent word lines on the substrate, forming source/drain impurity regions in the active regions adjacent to both sides of each of the word lines, forming insulating sidewalls on both sides of each of the word lines, forming capacitor node plugs and bit line contact plugs between the word lines and active regions after implanting impurity ions into a conductive layer deposited on the substrate including the word lines, forming a plurality of bit lines in a direction perpendicular to the word lines with a predetermined interval between adjacent bit lines by forming bit line contact holes contacting the bit line contact plugs in a first insulating interlayer deposited on the substrate, forming storage electrode contact holes to expose the capacitor node plugs in a second insulating interlayer deposited over the substrate, and subjecting the storage electrode contact holes to heat treatment before implanting impurity ions through the storage electrode contact holes into the active regions to grow the storage electrodes.


REFERENCES:
patent: 5959326 (1999-09-01), Aiso et al.
patent: 6187659 (2001-02-01), Ying et al.

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