Method for fabricating a semiconductor integrated circuit struct

Details Method for fabricating a semiconductor integrated circuit struct Method for fabricating a semiconductor integrated circuit struct

1988-10-17

1989-09-26

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156653, 156657, 1566591, 156662, 357 239, 357 53, 357 59, 437 41, 437 56, 437 59, 437228, 437233, 437239, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

048697818

ABSTRACT:
A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C. during which controllable quantities of the polycrystalline silicon are consumed. After removal of the thermally grown oxide, polycrystalline silicon portions are obtained with length and thickness dimensions reduced by a desired amount. If polycrystalline silicon portions are to be reduced only in length, the horizontal surfaces of these portions are protected during oxidation by a cap. The cap may include a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-relieve layer. The method is particularly useful in forming a submicrometer length gate electrode of a field effect transistor.

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