Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-03-01
2011-03-01
Brewster, William M (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S128000, C438S129000, C438S630000, C438S633000, C438S634000, C257S208000, C257S211000, C257S775000
Reexamination Certificate
active
07897499
ABSTRACT:
A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.
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Office Action issued from the Korean Patent Office on Nov. 15, 2007.
M.S. Lee et al., “Highly Manufacturable Landing Plug Contact Formation for 80nm Technology and Beyond,” The 12thKorean Conference on Semiconductors, pp. 433-434 and partial Table of Contents (2005).
Lee Jae-Young
Lee Min-Suk
Baptiste Wilner Jean
Brewster William M
Hynix / Semiconductor Inc.
IP & T Group LLP
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