Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2001-12-27
2002-11-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S664000, C438S682000, C438S299000
Reexamination Certificate
active
06486048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device capable of forming silicide suitable for highly integrated semiconductor devices.
2. Description of the Related Art
As is generally known, in order to reduce contact resistance and sheet resistance of source/drain regions in CMOS, a method has been proposed that a silicide layer is formed by using titanium Ti, cobalt Co or nickel Ni having low resistivity and contact resistance in the source/drain regions.
The formation of silicide will be described below, using as an example formation of cobalt silicide. First, a cobalt layer Co is deposited on a substrate including source/drain regions. The cobalt layer has low resistivity, below 18 &mgr;&OHgr;/cm, and improved thermal stability.
Subsequent to deposition, the cobalt layer Co is subjected to a first Rapid Thermal Process (RTP) at a temperature below 650° C., thereby forming an intermediate phase cobalt silicide, CoSi.
Subsequently, the cobalt layer Co is selectively removed, in accordance with a wet etch process, so as to retain CoSi only on the source/drain. A second RTP is performed on the remaining cobalt layer Co at a temperature of 650~750° C., thereby obtaining a desirable cobalt silicide layer, CoSi
2
.
However, the cobalt silicide layer Cosi
2
has a thickness that is greater than desirable by about 3~4 times, compared with that of the early stage and the surface is very rugged since the Cobalt is diffused, thereby rapidly generating a reaction with the silicon Si. Therefore, the cobalt silicide layer CoSi
2
has a higher resistance than either titanium silicide or nickel silicide.
As semiconductor devices have become highly integrated, it became necessary to develop a shallow junction. However, it is difficult to apply the cobalt silicide and nickel silicide NiSi
2
onto the semiconductor device having the shallow junction since the semiconductors have a heavy thickness and a rugged surface.
Using titanium silicide TiSi
2
provides better conditions than when using cobalt silicide or nickel silicide. However, it is also difficult to apply titanium silicide to a semiconductor device, since it presents a rough surface. In particular, when it is applied to a device having a line width below 0.25 □, contact resistance is remarkably increased and when it is applied to a highly integrated memory device over 1 Gigabit DRAM, a problem of current leakage develops.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above-mentioned problems and the object of the present invention is to provide a method of fabricating a semiconductor device capable of forming a silicide having a thin thickness and smooth surface by decreasing the speed of metal diffusion.
In order to accomplish the above object, the present invention comprises the steps of: sequentially forming a conductive oxide layer and a metal layer on a substrate having a gate and source/drain regions; performing a first thermal treatment on the resulting structure; selectively removing the metal layer to retain the metal layer over only the part corresponding to the source/drain regions; forming an intermediate phase by etching the conductive oxide layer with the remaining metal layer employed as a mask; and forming a silicide layer by performing a second thermal treatment on the substrate including the intermediate phase.
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patent: 5567652 (1996-10-01), Nishio
patent: 5744832 (1998-04-01), Wolters et al.
patent: 6100181 (2000-08-01), You et al.
patent: 6214710 (2001-04-01), Park et al.
patent: 09251967 (1997-09-01), None
patent: 10008245 (1998-01-01), None
patent: 10012878 (1998-01-01), None
patent: 10321850 (1998-12-01), None
patent: 11044223 (1999-02-01), None
Hynix / Semiconductor Inc.
Ladas & Parry
Niebling John F.
Pompey Ron
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