Method for fabricating a semiconductor device having a planar su

Details Method for fabricating a semiconductor device having a planar su Method for fabricating a semiconductor device having a planar su

1993-02-02

1994-07-12

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437195, 437228, 51218R, 51283R, H01L 2144

Patent

active

053285530

ABSTRACT:
A planar surface (24) is obtained in a semiconductor device (10) having regions of differing material composition by means of a non-selective planarization process. The non-selective planarization process removes insulating material and conductive material at substantially the same rate. In one embodiment of the invention, stud vias (22) are formed by the removal of portions of a conductive layer (20) overlying the surface of an interlevel dielectric layer (16). Once the conductive layer (20) has been removed, the planarization process is continued and surface portions of the interlevel dielectric layer (16) are also removed. Upon completion of the process a planar surface (24) is formed having regions of conductive material and insulating material.

REFERENCES:
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patent: 4944836 (1990-07-01), Beyer et al.
patent: 5006484 (1991-04-01), Harada
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patent: 5084416 (1992-01-01), Ozaki et al.
Research Disclosure, Aug. 1992/647, "Planarization of Tungsten Filled Vias with Stringent Topography", Disclosed Anonomously.
W. Patrick et al., "Application of Chemical Mechanical Polishing to the Fabrication of VLSI . . . ", J. Electrochem. Soc., vol. 138, No. 6, Jun. 1991, pp. 1778-1784.
C. Kaanta et al., "Dual Damescene: A ULSI Wiring Technology", VMIC Conference--IEEE, Jun. 11-12, 1991, pp. 144-152.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, CA, 1990, pp. 253.

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