Method for fabricating a semiconductor device

Details Method for fabricating a semiconductor device Method for fabricating a semiconductor device

2002-11-15

2004-09-07

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S118000, C438S006000, C438S238000, C438S253000, C438S622000, C438S629000, C438S942000, C716S030000, C716S030000, C430S005000, C430S030000, C430S311000

Reexamination Certificate

active

06787459

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to photolithography for use in fabrication of a semiconductor device, liquid crystal panel, and so forth, and in particular, to a method of fabricating a semiconductor device by means of multiple exposures, using a phase shift mask comprising apertures allowing light rays of two phases, one and the other substantially reversed therefrom, to pass therethrough, and an opaque area, and a second mask comprising apertures allowing light rays of a single phase to pass therethrough, and an opaque area.
2. Description of the Prior Art
Photolithography for use in the formation of patterns for semiconductor integrated circuits etc. includes a multiple exposure technique through the use of a phase shift mask in order to form patterns with a resolution below the resolution limit of a common photomask comprising apertures for light rays of a single phase, and an opaque area. This technique has been disclosed in Japanese Patent Publication No. 2650962, and U.S. Pat. No. 5,858,580. That is, against layout patterns including a pattern P
2
of which a fine line pattern as shown in
FIG. 2A
, and projected pattern accuracy are required, the pattern P
2
is formed in latent image by a first exposure with a phase shift mask, and other patterns are formed in latent image by a second exposure with a second mask (referred to hereinafter as a trim mask) comprising apertures for light rays of an identical phase, and an opaque area (or a substantially opaque area), forming thereafter a resist pattern through development. In order to implement the shape of the layout pattern as shown in
FIG. 2A
, latent images are formed by the first exposure with the phase shift mask comprising aperture pattern P
3
, P
4
, (an out of phase pair) with a phase shift of approximately 180°, disposed in such a way as to sandwich the pattern P
2
therebetween, as shown in
FIG. 2B
, within a wholly opaque area P
1
, and by the second exposure with the trim mask as shown in
FIG. 2C
, having opaque areas comprising a protection pattern P
5
representing regions for portions of the latent image formed by the first exposure, which are to be protected, and a pattern P
6
not to be formed in latent image by the first exposure.
This method, particularly application thereof to the fabrication of a transistor gate of a CMOS logic LSI, has been under extensive study, and is commonly called a phase shifter edge exposure method because a gate length pattern below the resolution limit, requiring dimensional accuracy and, fine pattern delineation is formed at an aperture edge (phase shifter edge) of a phase sift mask where phase shift becomes 180°.
In order to express 180° phase shift, respective apertures of the phase sift mask are assigned 0-degree phase or 180-degree phase hereinafter for the sake of convenience, and apertures with 0-degree phase assigned thereto are designated 0-degree shifter pattern, and apertures with 180-degree phase assigned thereto 180-degree shifter pattern. In case two apertures adjacent to each other are both the 0-degree shifter patterns or the 180-degree shifter patterns, this is referred to as a case of an identical phase (no phase shift) while in case one is the 0-degree shifter pattern, and the other is the 180-degree shifter pattern, this is referred to as a case of opposite phases or revered phases (phase shift exists). Shifter patterns prior to phase assignment are referred to as aperture patterns for phase shift patterns. Further, an opaque width between sifters represents a distance between two sifters, in the direction of a gate length and correction of the gate length can be implemented by varying the width. Furthermore, a shifter pattern width is a dimension of a shifter pattern, in the direction of the gate length, and a protection pattern width is a width of a protection pattern, in the direction identical to that for the shifter pattern width.
A method of automatically generating the phase sift mask and trim mask as described above from design layout data has been disclosed in Japanese Patent Publication No. 3148770, and U.S. Pat. No. 5,858,580. Japanese Patent Publication No. 3148770, and U.S. Pat. No. 5,858,580 describes that a fine pattern which is imaged with respective shifter edges is extracted, division into regions where shifter patterns are disposed and other areas is made, and a 0-degree shifter pattern and a 180-degree shifter pattern are generated on both sides of the respective fine patterns as extracted.
Further, there can be cases where dimensions of resist patterns which should be identical in dimension undergo variation depending on a shifter pattern width or dimensional difference occurs to the gate patterns at the time of etching gate material depending on inconsistency in density of the resist patterns. Deformation and dimensional variation in a photolithography process are generally called an optical proximity effect, however, herein a proximity effect is meant to include pattern deformation and dimensional variation as well, taking place in an etching process. There is available proximity effect correction as a method of causing the shape of a layout pattern to be varied in advance in order to cope with the pattern deformation and dimensional variation, caused by the proximity effect. The proximity effect correction by the phase shifter edge exposure method, in particular, is described in Proceedings of SIPE, Vol. 3873 (1999), pp. 277-287, and Proceedings of SIPE, Vol. 4000 (2000), pp. 1062-1069.
SUMMARY OF THE INVENTION
In Japanese Patent Publication No. 3148770, and U.S. Pat. No. 5,858,580, no consideration is given to phases of shifter patterns having no fine patterns which are imaged with shifter edges in-between upon generation of the shifter patterns. For example, there are cases where adjacent shifter patterns will have an identical phase at spots without a pattern P
2
therebetween as shown in FIG.
3
B. However, when comparing results of exposure with a mask of irregular phase assignment as shown in
FIG. 3B
with results of exposure with a mask with 0-degree phase assigned shifter pattern and 180-degree phase assigned shifter pattern, alternately aligned as shown in
FIG. 1B
, it is found that a dimension of a pattern P
2
which is imaged with a shifter edge in the former case differs from the same in the latter case. As a result, fluctuation in dimension within a chip increases. For example, assuming that a width of a fine pattern, which is imaged with a shifter edge, is 120 nm, and a shifter pattern width is 500 nm, dependency of a shifter edge dimension after exposure with a phase shift mask and development on a focus position is as shown in FIG.
23
.
FIG. 23
shows that there is deviation between a focus center position of a phase shift mask of periodic phase assignment with 0-degree phase assigned shifter pattern and 180-degree phase assigned shifter pattern, alternately aligned as shown in
FIG. 1B
, and a focus center position of a phase shift mask of non-periodic phase assignment as shown in FIG.
3
B. If mixture of two areas, periodic phase assignment area and non-periodic phase assignment area, exists within a chip, a common focus region enabling a pattern within a desired dimension, 120 nm±10 nm, to be generated becomes extremely small. The greater aberration of an exposure system, the more pronounced this phenomenon becomes.
Further, in Japanese Patent Publication No. 3148770, and U.S. Pat. No. 5,858,580, placement of shifter patterns is limited to both sides of a fine pattern which is imaged with a shifter edge. For this reason, there occurs a difference between a dimension of a pattern which is imaged with a shifter edge positioned at the center of a region R
1
where shifter patterns are periodically placed a shown in
FIG. 4
, and a dimension of a pattern which is imaged with a shifter edge positioned in a region R
2
where only a pair of shifter patterns with mutually opposite phases assigned thereto, respectively, are placed. This problem has not been descri

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