Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2001-07-06
2003-12-09
Thompson, Craig (Department: 2873)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S462000
Reexamination Certificate
active
06660617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and particularly to a method for isolating individual devices. More particularly, the present invention relates to a method for fabricating a semiconductor device which has good polishing characteristics for a STI (Shallow Trench Isolation) method which forms isolating regions using a CMP (Chemical Mechanical Polishing) method.
2. Description of the Related Art
In recent years, semiconductor devices are becoming more highly integrated and individual elements are becoming finer. Individual elements in a semiconductor device are isolated from one another by an insulator filled in shallow trenches formed in a semiconductor substrate. This is a so-called STI method. Various processes are known for the STI method. For example, such a process is known in which: (i) a silicon oxide film and a silicon nitride film are sequentially laminated on a silicon wafer; (ii) the silicon nitride film and the silicon oxide film are sequentially etched to form a pattern using a resist pattern for photolithography as a mask; (iii) trenches are etched in the silicon substrate; (iv) a thermal oxide film is formed on inner walls of the trenches by thermal oxidation; (v) an oxide film is formed on the entire surface of the silicon wafer by a CVD method so that the trenches are filled with the oxide film; (vi) the oxide film formed on the silicon nitride film is removed by the CMP method using the silicon nitride film as a stopper in order to leave the oxide film only in the trenches; and (vii) the silicon nitride film is removed using hot phosphoric acid.
A wafer usually has a marking region besides a device region (effective chip region), and a wafer history is marked in this marking region by printing or the like. The marking is carried out, for example, by a laser. After this marking, the process of the STI method is carried out as described above (formation of the nitride film and the oxide film, and the CMP and the like thereafter).
The marking is carried out, for example, by dot printing using a laser (see
FIG. 6
; hereinafter, a portion in the marking region having such dot prints is referred to as a “marking portion”).
FIG. 6
also shows a sectional form of the marking portion after the CMP, and it can be seen that protrusions of about 1 &mgr;m in height are still left after the CMP, and openings are widened.
When the wafer having the marking portion as described above is subjected to the CMP, a polishing pressure applied to the wafer from a polishing pad varies at the marking portion and at a peripheral portion thereof, which produces portions which are excessively polished and insufficiently polished. Also in the effective chip region, a polishing pressure applied to effective chips adjacent to the marking region (adjacent effective chips) differs from that applied to other effective chips. That is, the polishing pressure applied to the entire effective chip region is not even. This causes insufficient polishing at the effective chips adjacent to the marking region, and the oxide film on that portion is not removed sufficiently and therefore remains. As a result, when a process to remove the nitride film using hot phosphoric acid in the STI method is carried out, the oxide film acts as a mask, and therefore the nitride film under that is not removed. This is a problem because a complete isolation structure is not obtained.
Now, the above described problem is explained in detail with reference to the figures.
FIG. 7A
is a conceptual illustration of a sectional structure in the vicinity of a peripheral potion of a wafer in a state in which a nitride film and an oxide film are formed as described above after a marking is carried out in a marking region of the wafer. This figure shows, as listed from the outermost peripheral portion, a marking region, a grid line (G/L) region, and a device region of effective chips adjacent to the marking region. In
FIG. 7A
, the reference numeral “
1
” designates a wafer substrate, “
2
” designates trenches, “
3
” designates the nitride film, “
4
” designates the oxide film and “
5
” designates a raised portion (protrusion) of a dot of a marking portion (a hole at the center of the dot is not shown).
Next, as shown in
FIG. 7B
, when the wafer is pressed by a polishing pad
6
and polished in a state in which polishing slurry
7
exists between the wafer
1
and the polishing pad
6
, the polishing pad elastically deforms to conform to the shape of the protrusion existing on the surface of the wafer. At this time, the polishing pressure is distributed in accordance with an amount of deformation of the pad. The polishing pressure concentrates particularly at the protrusion of the marking portion, and is dispersed and reduced at the peripheral area of the marking portion. At a further outer area thereof, the polishing pressure concentrates because of a rebound of the pad. Then, the polishing pressure is gradually balanced toward the device side.
Therefore, the polishing pressure concentrates at the raised portion produced by the marking and at the rebound portion, while it is reduced at the peripheral area of the marking portion and at the device region (adjacent effective chips).
Since a polishing speed of a film varies according to changes of the polishing pressure, it is increased at the protrusion of the marking portion and at the rebound portion, and is reduced at the device region. Consequently, in the middle stage of the polishing, as shown in
FIG. 7C
, portions which are highly pressed are polished, but the device region is not yet polished. As the polishing proceeds, i.e., together with the reduction of differences in level, the difference in the polishing speed is also reduced. However, once differences in the thickness of the film to be polished between excessively polished regions and insufficiently polished regions have become pronounced, they cannot be reduced.
Therefore, in the late stage of the polishing, as shown in
FIG. 7D
, the difference between the excessively polished regions and the insufficiently polished regions is significant, and a surface of the silicon substrate is exposed at the marking portion, while the oxide film is left at the adjacent effective chip region. Neither are desirable for the STI structure. This residual oxide film causes device defects since the oxide film left at the surface acts as a mask when the nitride film is removed by the hot phosphoric acid treatment after the CMP, and the films (oxide film
itride film) are locally left (see FIG.
7
E).
SUMMARY OF THE INVENTION
In view of the aforementioned, an object of the present invention is to fabricate a semiconductor device having a normal STI structure. The present invention eliminates the problem of insufficient polishing of effective chips adjacent to a marking region of a wafer by improving the environment of the marking region so that a substantially equal polishing pressure is applied to the entire effective chip region at polishing even wherein a conventional marking method is employed.
The above object is accomplished by providing a method for fabricating a semiconductor device having the following aspects.
A first aspect of the present invention is a method for fabricating a semiconductor device having an isolation structure, the method comprising: (a) providing a wafer having a device region including a plurality of chips, a grid line region and a marking region; (b) processing the marking region of the wafer for achieving a substantially equal pressure applied to the chips during surface polishing of the wafer; (c) creating a mark in the marking region; (d) depositing a nitride film on the surface of the wafer, and thereafter an oxide film; and (e) removing the oxide film by polishing the surface of the wafer.
A second aspect of the present invention is a method for fabricating a semiconductor device, the method comprising: (a) preparing a wafer having a device region and a marking region on a surface thereof, wherei
Oki Electric Industry CO Ltd.
Rabin & Berdo P.C.
Thompson Craig
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