Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-09-26
2002-12-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S778000
Reexamination Certificate
active
06492198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a redistributed chip size package and a wafer-level method for manufacturing the same.
2. Description of the Related Arts
A goal of the electronic industry is the miniaturization of semiconductor devices. This goal is important in semiconductor packaging. A semiconductor package is a structure including an IC chip sealed in a plastic resin or a ceramic with external terminals that allow connection and use of the chip in an electronic device. Such packages are typically much larger than the chips, and engineers have made great efforts to reduce IC packages to almost the same size as IC chips. An advancement in packaging technology is the Chip Scale Package (also called a Chip Size Package, CSP). A Wafer Level CSP (WL-CSP) is characterized in that multiple packages are collectively assembled and manufactured at the wafer level.
The WL-CSP typically uses flip chip bonding. For the flip chip bonding, a redistribution technique connects aluminum pads on the chip to bigger “rerouted” pads at different positions. External connecting electrodes such as solder balls are on respective rerouted pads. In redistributing the pads and forming the solder balls, a series of processes for manufacturing packages are performed at wafer level.
As known well, a semiconductor wafer commonly includes multiple integrated circuit chips formed on a semiconductor substrate, e.g., a silicon wafer.
FIG. 1
schematically shows a wafer
10
, and
FIG. 2
is an enlarged plan view of a portion “A” of FIG.
1
. As shown in
FIGS. 1 and 2
, each chip
20
has a plurality of chip pads
22
on an upper surface, and scribe lines
14
are between integrated circuit chips
20
on the wafer
10
. Passivation layer
24
covers the upper surface of the chip
20
except for the chip pads
22
.
FIG. 3
shows a plurality of chip size packages
30
manufactured at the wafer level. External connecting electrodes
36
of
FIG. 3
, which electrically connect to the chip pads
22
of the chips
20
of
FIG. 2
, have positions that differ from those of chip pads
22
. As described above, the position of each pad for the external connecting electrode
36
is offset from the corresponding chip pad
22
through the rerouting. Sawing the wafer
10
of
FIG. 3
along the scribe lines
14
separates individual packages
30
.
FIG. 4
show a cross-section of a portion of the conventional wafer level chip size package
30
. As shown in
FIG. 4
, a chip pad
22
and the passivation
24
are on the upper surface of the semiconductor substrate
12
. A first polymer layer
31
that absorbs stress and serves a dielectric function is on the passivation
24
, and under barrier metal (UBM) layers
32
are on the chip pads
22
and the first polymer layer
31
. A redistribution pattern
33
is on the UBM layers
32
, and a second polymer layer
34
is on the redistribution pattern
33
. The second polymer layer
34
protects the redistribution pattern
33
from external environmental stresses. An external connecting electrode
36
connects to a portion of the redistribution pattern
33
via other UBM layers
35
.
Usually, the redistribution pattern
33
is copper (Cu), which has a high electrical conductivity. However, oxygen (O
2
) in the atmosphere oxidizes or reacts with copper, particularly at high temperature such as used when curing the polymer layer
34
. These characteristics of copper reduce the adhesive strength to other materials. Particularly, in the structure of the wafer level chip size package
30
of
FIG. 4
, oxidation of the copper reduces the adhesive strength between the copper redistribution pattern
33
and the second polymer layer
34
, and therefore degrades the reliability of the package.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, the adhesive strength between a copper redistribution layer and a polymer layer is increased to improve the reliability of a WL-CSP package.
In one embodiment of the invention, a semiconductor device includes a semiconductor chip, a first polymer layer, one or more first under barrier metal layers, a copper redistribution pattern, a barrier metal, a second polymer layer, and external connecting electrodes. The semiconductor chip includes a semiconductor substrate, a passivation formed thereon, and a plurality of chip pads exposed through the passivation. The first polymer layer is on the passivation. The first under barrier metal (UBM) layers form a pattern on the chip pads and the first polymer layer. The copper redistribution pattern is on the first UBM layers and electrically connected to the chip pads. The second polymer layer is on the first polymer layer and the copper redistribution pattern,. The barrier metal is on the copper redistribution pattern. The external connecting electrodes are on portions of the copper redistribution pattern or the barrier metal that the second polymer layer exposes.
The barrier metal includes a chrome (Cr), a nickel (Ni), or a nickel-chrome (Ni—Cr) layer, and preferably has a thickness between approximately 0.1 &mgr;m and 50 &mgr;m. The barrier metal may further include a metal inner complex formed by reacting the surface of the Cr, Ni, or Ni—Cr layer with a silane or an azole group solution. Typically, the semiconductor device further includes second under barrier metal (UBM) layers under each of the external connecting electrodes. The first and the second polymer layers are typically selected from the group consisting of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), and epoxy.
In another aspect, an embodiment of the present invention provides a method for fabricating semiconductor devices. The method includes (A) providing a semiconductor wafer that includes a semiconductor substrate, a passivation thereon, and a plurality of chip pads exposed through the passivation, (B) forming a first polymer layer on the passivation, (C) forming first under barrier metal (UBM) layers on the chip pads and the first polymer layer, (D) forming a patterned copper redistribution pattern on the first UBM layers, said copper redistribution pattern being electrically connected to the chip pads, (E) forming a barrier metal on the copper redistribution pattern, (F) removing a portion of the first UBM layers that the patterned copper redistribution pattern exposes, (G) forming a second polymer layer on the first polymer layer and the copper redistribution pattern, and (H) forming a plurality of external connecting electrodes on a portion of the copper redistribution pattern exposed through the second polymer layer.
The step (E) can include plating chrome (Cr) or nickel (Ni), or nickel (Ni) and chrome (Cr) in order. After plating, the step (E) can further include reacting the surface of the Cr or Ni layers with a silane or an azole group compound solution to form a metal inner complex. The silane compound is selected from the group consisting of vinyltriacetoxy silane, vinyltrichloro silane, vinyltrimethoxy silane, vinyltriethoxy silane, vinyltris (&bgr;-methoxy ethoxy) silane, N-&bgr;(amino ethyl)&ggr;-amino propyl methyl dimethoxy silane, N-&bgr;(amino ethyl)&ggr;-amino propyl trimethoxy silane, N-&bgr;(amino ethyl)&ggr;-amino propyl triethoxy silane, &ggr;-amino propyl trimethoxy silane, &ggr;-amino propyl triethoxy silane, N-phenyl-&ggr;-amino propyl trimethoxy silane, and &ggr;-chloro propyl trimethoxy silane. The azole compound is selected from the group consisting of polybenzimidazole, benzotriazole, 8-azaadenine, and 5-carboxylic benzotriazole. Before and after forming the external connecting electrodes, the method of the present invention can further include forming a second under barrier metal (UBM) layers under each of the external connecting electrodes and dividing the semiconductor wafer into individual packages by sawing.
REFERENCES:
patent: 4060828 (1977-11-01), Satonaka
patent: 4268849 (1981-05-01), Gray et al.
patent: 4742014 (1988-05-01), Hooper et al.
patent: 5391517 (1995-
Hoang Quoc
Samsung Electronics Co,. Ltd.
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