Method for fabricating a semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

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438631, 438760, H01L 213205

Patent

active

059181427

ABSTRACT:
A method for fabricating a semiconductor device, wherein, when a blanket of the planarization layer is deposited and thermally treated for its reflow after the formation of a metal gate electrode consisting of a CVD-TiN layer pattern and a W layer pattern on a semiconductor substrate, a gate oxide is formed at the interface between the CVD-TiN layer and the semiconductor substrate by the reaction of the moisture absorbed in the CVD-TiN layer with the Si of the substrate, without executing an additional process and, thus, the stress between the gate oxide and the metal layer is not high, so that the gate oxide can be prevented from being degraded, and the production yield and the reliability of device operation is improved.

REFERENCES:
patent: 5466629 (1995-11-01), Mihara et al.
patent: 5567651 (1996-10-01), Berti et al.

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