Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-15
2001-05-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S639000, C438S640000, C438S622000, C438S618000, C438S619000, C438S620000, C438S621000, C438S597000, C438S675000, C438S624000, C257S758000
Reexamination Certificate
active
06232220
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a semiconductor component having a low contact resistance with respect to n
+
-conducting or p
+
-conducting, heavily doped zones in a semiconductor body, in which at least one titanium-containing layer is provided in a contact hole between the heavily doped zone and a contact metal connected to an external supply line.
Such a method is disclosed in U.S. Pat. No. 5,225,357. In that case, n
+
-conducting or p
+
-conducting, heavily doped zones are present which are connected, in a contact hole, to an external supply line through at least one titanium-containing layer and a contact metal applied thereto. Halogen is introduced into the heavily doped zones in the vicinity of the contact hole in order to reduce the contact resistance with respect to the heavily doped zone.
Furthermore, the implantation of fluorine ions in n-conducting silicon is described in a paper entitled: “Formation of Surface Inversion Layer in F
+
-Implanted n-Type Silicon”, by C. H. Chu et al., in Journal of Crystal Growth, Vol. 103, No. 1/4 (June 1990), Amsterdam, NL, pages 188 to 196.
In contact holes, a titanium layer and/or a titanium nitride layer serves as a barrier layer or layers in order to avoid diffusion from the semiconductor body into a contact layer, which is preferably composed of tungsten. Contacts of that type having a titanium/titanium nitride/tungsten layer sequence are provided, for example, on source and drain zones of CMOS transistors.
The contact resistance is undesirably large, particularly in contact holes having what is referred to as a high aspect ratio, that is to say a high value of the ratio between height and width of the contact hole. The same also applies to siliconized diffusion zones, that is to say zones formed by the reaction of silicon with titanium to form titanium silicide.
Increasing the layer thickness of the titanium layer would be conceivable for reducing the contact resistance. However, that is undesirable since the necessary layer thickness of the titanium layer should actually be reduced if only for reasons of saving material and microminiaturization.
Finally, thin oxide layers which are inevitably formed in the contact hole in the course of thermal processes also lead to disruptive effects and, in particular, to an increase in the contact resistance.
In addition to increasing the layer thickness of the titanium layer as mentioned above, consideration has also been given to collimated sputtering of titanium for forming the titanium layer, in order to ensure a reduction in the contact resistance. Another solution approach for decreasing the contact resistance is in the application of an additional sputtering and heat-treatment step for siliconizing the bottom of the contact hole. However, those two last-mentioned solution approaches for reducing the contact resistance, namely collimated sputtering of titanium and siliconization, are relatively complicated and have not yet achieved the desired results of a contact resistance which is sufficiently reduced in a simple manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a semiconductor component in which a contact resistance with respect to heavily doped or siliconized diffusion zones is decreased in a simple manner in conjunction with a reduced layer thickness of a titanium layer, which causes no disruptive effect of thin oxide layers and which overcomes the herein afore-mentioned disadvantages of the heretofore-known methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor component, which comprises producing an n
+
-conducting or p
+
-conducting, heavily doped or siliconized zone in a semiconductor body through a contact hole in a masking layer; implantating fluorine ions in the vicinity of the contact hole into a surface region of the heavily doped or siliconized zone; and subsequently applying at least one titanium-containing layer in the contact hole and applying a contact metal.
In the case of the semiconductor component according to the invention, fluorine is introduced into the heavily doped zone or siliconized zone by ion implantation. The fluorine then leads to an increased efficacy of the titanium which is subsequently sputtered into the contact hole. Any oxide layers in the contact hole which are formed in the course of thermal processes can be broken up by less titanium, and the formation of titanium silicide in the contact hole is promoted. Overall, the contact resistance is thus reduced.
In accordance with another mode of the invention, the fluorine is implanted with a dose of about 10
12
to 10
16
ions/cm
2
. A greater concentration of fluorine does not afford any further significant improvement in the contact resistance, whereas a lesser concentration does not sufficiently increase the efficacy of the sputtered titanium.
In accordance with a further mode of the invention, the layer sequence in the contact hole includes a titanium film, a titanium nitride film applied thereto, and a tungsten layer.
In accordance with an added mode of the invention, the fluorine ions are implanted into the semiconductor body through the contact hole at an accelerating voltage of about 5 to 50 keV, and a titanium layer and a tungsten layer are then applied to the semiconductor body in the contact hole in a conventional manner.
Implanting fluorine ions in the heavily doped or siliconized zone thus achieves an increased efficacy of the titanium which is sputtered into the contact hole. As a result, any oxide layers that are present are broken up by less titanium and the formation of titanium silicide in the contact hole is facilitated, thereby achieving an appreciable reduction in the contact resistance.
In accordance with a concomitant mode of the invention, there is provided a method which comprises applying the titanium film with a layer thickness of 10 to 100 nm, in particular 40 nm.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped zones, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5198373 (1993-03-01), Yoshino
patent: 5225357 (1993-07-01), Ho
patent: 5296386 (1994-03-01), Aronowitz et al.
patent: 5466612 (1995-11-01), Fuse et al.
patent: 5498768 (1996-03-01), Nishitai et al.
patent: 5591672 (1997-01-01), Lee et al.
patent: 5691220 (1997-11-01), Ohnishi et al.
patent: 5714788 (1998-02-01), Ngaoaram
patent: 5960321 (1999-09-01), Hsieh et al.
patent: 5963812 (1999-10-01), Kataoka et al.
patent: 02027716 (1988-07-01), None
patent: 05021748 (1991-07-01), None
patent: 7249763 (1995-09-01), None
S. Wolf & R. Tauber,Silicon Processing, Lattice press, 198, p. 280.*
“A Highly Reliable Interconnection for a BF2+-Implanted Junction Utilizing a TiN/Ti Barrier Metal System”, Takeo Maeda et al., IEEE Transactions on Electron Devices, vol. EC-34, No. 3, Mar. 1987, pp. 599-606.
“Effects of BF2+-implants on titanium silicide formation by rapid thermal annealing”, J.S. Choi et al., J. Appl. Phys. 72(1), Jul. 1, 1992, pp. 297-299.
“Collimated sputtering of TiN/Ti liners into sub-half-micrometer high aspect ratio contacts/lines”, R.V. Joshi et al., Appl. Phys. Lett. 61 (21), Nov. 23, 1992, pp. 2613-
Mahnkopf Reinhard
Penka Volker
Wurzer Helmut
Greenberg Laurence A.
Infineon - Technologies AG
Lee, Jr. Granvile D
Lerner Herbert L.
Smith Matthew
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