Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...
Reexamination Certificate
2002-10-04
2003-09-23
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With electric field controlling semiconductor layer having a...
C257S495000, C257S509000, C257S510000, C257S655000, C257S656000
Reexamination Certificate
active
06624494
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor power devices, and more particularly to a semiconductor power device such as a MOSFET and other power devices that use floating islands of oppositely doped material to form the voltage sustaining layer.
BACKGROUND OF THE INVENTION
Semiconductor power devices such as vertical DMOS, V-groove DMOS, and trench DMOS MOSFETs, IGBTs as well as diodes and bipolar transistors are employed in applications such as automobile electrical systems, power supplies, motor drives, and other power control applications. Such devices are required to sustain high voltage in the off-state while having low on-resistance or a low voltage drop with high current density in the on-state.
FIG. 1
illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer
101
formed over an N+ doped silicon substrate
102
contains p-body regions
105
a
and
106
a
, and N+ source regions
107
and
108
for two MOSFET cells in the device. P-body regions
105
and
106
may also include deep p-body regions
105
b
and
106
b
. A source-body electrode
112
extends across certain surface portions of epitaxial layer
101
to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-type epitaxial layer
101
extending to the upper semiconductor surface in
FIG. 1. A
drain electrode is provided at the bottom of N+ doped substrate
102
. An insulated gate electrode
118
comprising insulating and conducting layers, e.g., oxide and polysilicon layers, lies over the channel and drain portions of the body.
The on-resistance of the conventional MOSFET shown in
FIG. 1
is determined largely by the drift zone resistance in epitaxial layer
101
. Epitaxial layer
101
is also sometimes referred to as a voltage sustaining layer since the reverse voltage applied between the N+ doped substrate and the P+ doped deep body regions is sustained by epitaxial layer
101
. The drift zone resistance is in turn determined by the doping concentration and the thickness of epitaxial layer
101
. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer
101
must be reduced while the layer thickness is increased. The curve in
FIG. 2
shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as the curve shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3
shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in Cezac et al.,
Proceedings of the ISPSD
, May 2000, pp. 69-72, and Chen et al.,
IEEE Transactions on Electron Devices
, Vol. 47, No. 6, June 2000, pp. 1280-1285, which are hereby incorporated by reference in their entirety. This MOSFET is similar to the conventional MOSFET shown in
FIG. 1
except that it includes a series of vertically separated P− doped layers
310
1
,
310
2
,
310
3
, . . .
310
n
(so-called “floating islands”), which are located in the drift region of the voltage sustaining layer
301
. The floating islands
310
1
,
310
2
,
310
3
, . . .
310
n
produce an electric field that is lower than for a structure with no floating islands. The lower electric field allows a higher dopant concentration to be used in the epitaxial layer that in part, forms the voltage sustaining layer
301
. The floating islands produce a saw-shaped electric field profile, the integral of which leads to a sustained voltage obtained with a higher dopant concentration than the concentration used in conventional devices. This higher dopant concentration, in turn, produces a device having an on-resistance that is lower than that of a device without one or more layers of floating islands.
The structure shown in
FIG. 3
can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus a structure that uses multiple epitaxial deposition steps is expensive to manufacture.
Accordingly, it would be desirable to provide a method of fabricating a power semiconductor device such as the MOSFET structure shown in
FIG. 3
, which method requires a minimum number of epitaxial deposition steps so that the device can be produced less expensively.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
The power semiconductor device formed by the inventive method may be selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a bipolar transistor, and diodes.
In accordance with another aspect of the invention, a power semiconductor device is provided. The device includes a substrate of a first conductivity type and a voltage sustaining region disposed on the substrate. The voltage sustaining region includes an epitaxial layer having a first conductivity type and at least one trench located in the epitaxial layer. At least one doped layer having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. A filler material is also provided, which substantially fills the trench. At least one region of the second conductivity is disposed over the voltage sustaining region to define a junction therebetween.
REFERENCES:
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4569701 (1986-02-01), Oh
patent: 4711017 (1987-12-01), Lammert
patent: 5108783 (1992-04-01), Tanigawa et al.
patent: 5216275 (1993-06-01), Chen
patent: 5701026 (1997-12-01), Fujishima et al.
patent: 6310365 (2001-10-01), Chen
patent: 6495421 (2002-12-01), Luo
patent: 2001/0026977 (2001-10-01), Hattori et al.
N. Cezac et al., “A New Generation of Power Unipolar Devices: the Concept fo the Floating Islands MOS Transistor (FLIMOST),” Proceedings of the ISPSD, May 2000, pp. 69-72.
X. Chen et al., “A Novel High-Voltage Sustaining Structure with Buried Oppositely Doped Regions,” IEEE Transactions on Electron Devices, vol. 47, No. 6, Jun. 2000, pp. 1280-1285.
Blanchard Richard A.
Guillot Jean-Michel
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
Niebling John F.
Pompey Ron
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