Fishing – trapping – and vermin destroying
Patent
1991-08-06
1993-12-07
Thomas, Tom
Fishing, trapping, and vermin destroying
437 52, 437918, 148DIG136, H01L 2170
Patent
active
052683257
ABSTRACT:
A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.
REFERENCES:
patent: 4592128 (1986-06-01), Bourassa
patent: 4604789 (1986-08-01), Bourassa
patent: 4948747 (1990-08-01), Pfiester
patent: 4965214 (1990-10-01), Choi et al.
patent: 5126279 (1992-06-01), Roberts
Liou Fu-Tai
Spinner III Charles R.
Hill Kenneth C.
Jorgenson Lisa K.
Nguyen Tuan
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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