Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-03-29
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S591000, C438S257000
Reexamination Certificate
active
06461949
ABSTRACT:
FIELD OF THE INVENTION
The present invention provides a method of fabricating a gate in a nitride read only memory (NROM).
DESCRIPTION OF THE PRIOR ART
A read only memory (ROM) device, composed of a plurality of memory cells, is a kind of semiconductor wafer device that functions in data storage. The ROM device is widely applied to computer data storage and memory. Depending on the method of storing data, the ROM can be divided into several types such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and an electrically erasable programmable ROM (EEPROM).
Differing from other types of ROMs that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to the highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped within to form an unequal concentration distribution to hasten data reading speed and to avoid current leakage.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of a standard structure of an NROM according to the prior art. A semiconductor wafer
10
comprises a P-type silicon substrate
12
, two N-type doped areas
14
,
16
positioned on the surface of the silicon substrate
12
, an ONO dielectric structure
24
, and a gate conductor layer
26
positioned on the ONO dielectric structure
24
. The ONO dielectric structure
24
is composed of a bottom oxide layer
18
, a silicon nitride layer
20
and a top oxide layer
22
.
Please refer to FIG.
2
and FIG.
3
. FIG.
2
and
FIG. 3
are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG.
1
. As shown in
FIG. 2
, according to the prior art for fabricating a gate of the NROM, a semiconductor wafer
30
comprising a P-type silicon
32
is first provided. A high temperature oxidation process is then performed to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer
34
on the surface of the silicon substrate
32
. Next, a low-pressure chemical vapor deposition (LPCVD) is used to deposit a silicon nitride layer
36
with a thickness of 50-150 angstroms on the bottom oxide layer
34
. An annealing process is then used under a high temperature of 950° C. for a duration of 30 minutes to repair the structure of the silicon nitride layer
36
. As well, water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of the 50-150 angstroms as a top oxide layer
38
. The bottom oxide layer
34
, the silicon nitride layer
36
and the top oxide layer
38
compose the ONO dielectric structure
40
on the surface of the silicon substrate
32
.
As shown in
FIG. 3
, a photolithographic and etching process is performed to form a gate pattern in the top oxide layer
38
and silicon nitride layer
36
. An ion implantation process is then performed to form a plurality of doped areas
42
as a source and drain in the MOS transistor. Thereafter, a thermal oxidation process is used to form a field oxide (FOX)
44
on the surface of the source/drain to isolate each silicon nitride layer
36
. Finally, a doped polysilicon layer
46
is deposited as a gate conductor layer.
According to the prior art for forming a top oxide layer, the process requires higher temperature and thermal budget to form an oxide layer on the surface of the nitride compound. Thus, not only is greater cost needed, but the higher temperature may lead to the degradation of the gate oxide layer and affect the reliability of the NROM. Moreover, because of the low dielectric constant of silicon oxide, the top oxide layer comprises lower coupling ratio and higher control gate voltage.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a gate fabrication method of an NROM with high dielectric constant of the top oxide layer to solve the above-mentioned problems.
In accordance with the claim invention, the method first forms a bottom oxide layer and a silicon nitride layer on the surface of a silicon substrate in the semiconductor wafer, respectively followed by injecting a tantalum penta ethoxide (Ta(OC
2
H
5
)
5
), under the condition of 300 mTorr and 200-650° C., to deposit a tantalum pentaoxide (Ta
2
O
5
) layer as a top oxide layer.
It is an advantage of the present invention that the present invention uses tantalum pentaoxide, having a high dielectric constant, as a top oxide layer of the ONO dielectric layer, to thereby increase the coupling ratio, reduce both the control gate voltage and thermal budget of the fabrication, and to avoid the problem of gate oxide degradation due to high temperature so as to improve the production yield of the semiconductor wafer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5552337 (1996-09-01), Kwon et al.
patent: 6251761 (2001-06-01), Rodder et al.
Chang Kent Kuohua
Chen Chia-Hsing
Hsu Winston
Le Dung A
Macronix International Co. Ltd.
Nelms David
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