Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2007-12-07
2009-12-15
Hoang, Quoc D (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C257S251000, C257SE21050, C257SE21051
Reexamination Certificate
active
07632726
ABSTRACT:
A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.
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Heying, Benjamin, Smorchkova, loulia, Gambin, Vincent and Coffie, Robert, U.S. Utility Patent Application entitled “Protective Layer in Fabrication Device”, U.S. Appl. No. 11/708,779, filed Feb. 21, 2007.
Coffie Robert
Gambin Vincent
Heying Benjamin
Smorchkova Ioulia
Hoang Quoc D
Miller John A.
Miller IP Group, PLC
Northrop Grumman Space & Mission Systems Corp.
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