Method for fabricating a MOS transistor

Details Method for fabricating a MOS transistor Method for fabricating a MOS transistor

2000-08-17

2002-07-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S692000

Reexamination Certificate

active

06423587

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a metal oxide semiconductor (MOS) transistor, and more particularly, to a method for fabricating a MOS transistor that has a T-shaped gate electrode.
2. Description of the Prior Art
With the progressive development of very large scale integration (VLSI) circuits, metal-oxide semiconductor (MOS) transistors that consume less power and that can be highly integrated are widely used in both the semiconductor and electronics industries. A MOS transistor typically comprises a MOS capacitor, and two doped regions which are complementary to the substrate, called a source and a drain. When a proper voltage is applied, MOS transistors can be used as a kind of switch to control the flow of electricity through a device. As the development of integrated circuits grows ever more complex and precise, controlling the manufacturing process of MOS transistors becomes an increasingly important issue.
Please refer to
FIG. 1
, which is a schematic diagram of a MOS transistor
20
according to the prior art. In the following description, an N-type MOS transistor is considered. For the prior art method of forming the MOS
20
, an active area (not shown) is defined on a silicon substrate (not shown) of a semiconductor wafer
10
, and then a shallow trench isolation (STI) structure
11
is formed on the silicon substrate, which surrounds the active area. P-type dopants are used to dope the semiconductor
10
. A thermal process is performed to drive the dopants into the substrate so as to form a P-well
12
. A thermal oxidation process and a thin film process are then performed on the semiconductor
10
to form a silicon dioxide layer and a doped polysilicon layer.
A photoresist layer (not shown) is coated onto the surface of the semiconductor wafer
10
, and a photolithographic process is performed on the photoresist layer to define the pattern of a gate
26
. Then a dry etching process is performed to form a gate oxide layer
22
and a gate electrode
24
of the gate
26
. The photoresist layer is then stripped. An ion implantation process is performed to form lightly doped drains (LDD)
14
, adjacent to the lateral sides of the gate
26
of the MOS transistor
20
. A chemical vapor deposition (CVD) process is then performed to deposit a silicon nitride layer (not shown) on the semiconductor wafer
10
, and an anisotropic dry etching process is performed to remove the silicon nitride layer down to the surface of the P-well
12
so as to form a spacer
28
on each lateral side of the gate
26
. Using the gate
26
and the spacers
28
as hard masks, an ion implantation process is performed to dope N-type dopants into the P-well
12
so as to form a source
16
and a drain
18
of the MOS transistor
20
.
However, in semiconductor processes, the the ion implantation steps, or the production of doped areas, such as P-well or N-well, are repeatedly performed on the semiconductor wafer
10
to form the MOS transistor
20
and other devices. The ion implantation process is a bombarding of ionized dopants into the semiconductor wafer
10
, and during this process the edges of the top of a dielectric layer in the STI
11
may be destroyed. Additionally, before the production of the gate oxide layer
22
, an SC-1 (standard cleaning 1) cleaning solution, a product of RCA (Radio Corporation of America), is usually applied to clean the surface of the semiconductor wafer
10
so as to remove impurities or poor quality silicon oxide layers. When the cleaning process is performed, the dielectric layer in STI
11
, or the silicon substrate of the surface of the semiconductor wafer
10
can be damaged, especially those regions in the STI
11
destroyed by the ion implantation process.
Please refer to FIG.
2
.
FIG. 2
is a schematic diagram of a recess
23
in the edge of the top of a dielectric layer filling the prior art STI
11
. In the above description, to maintain the surface cleanliness of the semiconductor wafer
10
, the semiconductor wafer
10
undergoes repeated cleaning steps, which creates the recess
23
at the edges of the top of the dielectric layer in the STI
11
. And when an etching process is then performed on the gate
26
, the doped polysilicon layer will remain in the recess
23
, destroying the insulated effect of the STI
11
, and adversely affecting the quality of the entire semiconductor product.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a MOS transistor on a semiconductor wafer so as to promote the electrical performance of the MOS transistor. The present invention also avoids the formation of recesses at the edges of the top of a dielectric layer of an STI that surrounds the MOS transistor, thus resolving the above-mentioned problem.
In a preferred embodiment, a mask layer is formed on a predetermined area within the active area, and then a first ion implantation process is performed on the silicon substrate not covered by the mask layer within the active area so as to form a lightly doped drain (LDD) of the MOS transistor. A first dielectric layer is formed on the surface of the semiconductor wafer, and a photoresist layer with a opening is formed on the surface of the first dielectric layer. An etching process is then performed through the opening of the photoresist layer so as to form a concavity with a diameter that is larger than that of the opening, and a gap with a length that is approximately equal to the diameter of the opening, on the surface of the first dielectric layer below the opening. A second dielectric layer is then formed on the surface of the silicon substrate at the bottom of the gap, and a conductive layer is deposited to fill the concavity and the gap. Portions of the conductive layer and the first dielectric layer are removed so that the residual portions form a gate conductive layer whose vertical cross-section is approximately T-shaped. Finally, a second ion implantation process is performed to form the source and the drain of the MOS transistor on the silicon substrate within the active area to complete the MOS transistor.
In another preferred embodiment of this invention, a first dielectric layer and a conductive layer are formed on a predetermined area within the active area, and then the LDD of the MOS transistor is formed on the silicon substrate that is not covered by the first conductive layer. Then a second oxide layer, which is approximately flush with the top surface of the first dielectric layer, is formed on the surface of the semiconductor wafer, and a second conductive layer is formed on the surface of the second oxide layer. Portions of the second conductive layer and the second oxide layer are removed so that the residual second conductive layer and the first conductive layer form a T-shaped gate. Finally, the source and the drain of the MOS transistor are formed on the silicon substrate within the active area to complete the MOS transistor.
It is an advantage of the present invention that it provides a process to integrate high permittivity materials serving as the gate oxide layer of the MOS transistor. The MOS transistor of the present invention has a gate conductive layer with a vertical cross-section that is approximately T-shaped, and a spacer formed through a CVD oxide layer. This reduces both the thermal budget and the parasitic capacitance between the gate and the drain or between the gate and the source. Additionally, the present invention also efficiently avoids the phenomenon of recesses generated at the edges of the top of the dielectric layer in the STI structure surrounding the MOS transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 6100558 (2000-08-01), Krivokapic et al.
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