Method for fabricating a metal-oxide semiconductor device

Details Method for fabricating a metal-oxide semiconductor device Method for fabricating a metal-oxide semiconductor device

1998-11-06

2001-01-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S305000, C438S655000, C438S682000

Reexamination Certificate

active

06177336

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a metal-oxide semiconductor device (MOS) device.
2. Description of Related Art
A MOS device is the most elementary device in a integrated circuit (IC) device. A MOS transistor usually includes a gate structure, a source region, and a drain region. The gate structure further includes a gate oxide layer and a metal layer sequentially formed on a semiconductor substrate, such as a silicon substrate. The source region and the drain region are formed in the semiconductor substrate respectively at each side of the gate structure. Since the source region and the drain region is interchangeable, the source region drain region are usually called together as an interchangeable source/drain region.
Conventionally, before forming the gate structure of the MOS transistor, a global ion implantation process is necessarily performed over the semiconductor substrate so as to adjust a threshold voltage of the gate structure and form a capability of anti-punch-through. The gate structure, the source region and the drain region are then formed to accomplish the MOS transistor. The conductive layer of the gate structure usually includes a doped polysilicon layer and a metal silicide layer, which is also called a silicide layer. The polysilicon layer provides a better adhesion capability with the gate oxide layer, and the suicide layer provides a better conductivity. Combining these two layers, the metal layer of the gate structure is called a polycide layer.
In above, even through the global ion implantation process has its advantages, it also causes an extra junction capacitance of the source/drain region, resulting a larger AC resistance, which decreases a data transmission speed. Moreover, as the device integration continuously increases, the device dimension has reached to a deep sub-micron level. The conventional polycide layer of the gate structure therefore has larger resistance due to a reduced dimension. This also causes to decrease the data transmission speed. Furthermore, for a dual gate structure, which includes two gate structures abutting each other, the dopants of the doped polycide layers of each gate structure may inter-diffuse each other through the silicide layers of the dual gate structure, resulting in a drifting of the threshold voltage. Moreover, the silicide layers may be agglomerated as an annealing process is performed in a high temperature environment. The agglomeration phenomenon causes an instability of electrical properties of the gate structure. A conventional solution, called a selective local implantation process, to solve the above problems is proposed to take place of the global ion implantation process. A metal gate layer also takes place of the conventional silicide layer of the polycide gate structure. The conventional proposal is described in FIGS.
1
A-
1
D, which are cross-sectional views of a MOS transistor, schematically illustrating a conventional fabrication process of the MOS transistor.
In
FIG. 1A
, a semiconductor substrate
100
including a trench isolation structure
102
is provided. A photoresist layer
104
is formed on the substrate
100
and is patterned to expose a portion of the substrate
100
, where a gate structure is to be formed. Using the photoresist layer
104
as a mask, ion implantation processes are performed to form a threshold-voltage doped region
116
a
and an anti-punch-through region
116
b
in the substrate
100
below the threshold-voltage doped region
116
a.
In
FIG. 1B
, after removing the photoresist layer
104
, a gate oxide layer
106
, a polysilicon layer
108
, and a metal layer
110
are sequentially formed over the substrate
100
.
In
FIG. 1C
, the gate oxide layer
106
, the polysilicon layer
108
, and the metal layer
110
are patterned to respectively form a gate oxide layer
106
a
, a polysilicon layer
108
a
, and a metal layer
110
a
, all of which form a gate structure
109
, which is above the threshold-voltage doped region
116
a.
In
FIG. 1D
, a light ion implantation is performed to pre-form an interchangeable source/drain region between the gate structure
109
and the trench isolation structure
102
. A sidewall spacer
112
is formed on each sidewall of the gate structure
109
. Using the sidewall spacer
112
and the gate structure
109
as a mask, a heavy ion implantation is performed to accomplish an interchangeable source/drain region
114
in the substrate
100
at each side of the gate structure
109
. A MOS transistor with the selective local implantation process is therefore formed. The interchangeable source/drain region
114
has lightly doped drain (LDD) structure. The metal layer
110
a
in the gate structure
109
can solve those conventional issues of high gate resistance, polycide thermal instability, and inter-diffusion. The MOS transistor with the selective local implantation process can reduce the junction capacitance in order to increase operation of data transmission speed.
However, the metal layer
110
cannot be easily etched, and the etched metal particles from the metal layer
110
remaining a etching tank may cause an acid-tank contamination. A contaminated etching tank may affect subsequent etching performance. Moreover, the selective local implantation process needs an extra mask, which also needs a critical alignment accuracy. A low yield rate may occurs.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a MOS transistor so as to solve avoid an extra mask for performing a selective local implantation. An alignment inaccuracy from the extra mask is avoided.
It is another an objective of the present invention to provide a method for fabricating a MOS transistor so as to solve the issue of a difficulty of etching a metal layer included in a gate structure, and avoid an acid-tank contamination resulting from the etching process on the metal layer.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabricating a MOS transistor is provided. The improved method includes sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate, in which a sidewall spacer is also formed on each sidewall of the first-stage structure. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. The self-aligned selective local implantation process needs no an extra mask and its alignment so that fabrication difficulty of accuracy and fabrication cost are effectively reduced.
A conductive layer, such as a metal layer, is formed over the substrate to fill the opening. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure. Since the conductive layer is formed without including an etching process. There are no issues of difficult etching on the metal layer and acid-tank contamination during etching the metal layer, which issues may occurs in a conventional fabrication method.
In the foregoing, the interchangeable source/drain region may also include a formation of a self-aligned silicide (Salicide) layer on its top, and a formation of a barrier layer between the metal layer and the polysilicon layer.


REFERENCES:
patent: 5731239 (1998-03-01), Wo

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