Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2006-01-05
2009-02-03
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S175000, C257SE29317, C257S280000
Reexamination Certificate
active
07485514
ABSTRACT:
A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in the substrate.
REFERENCES:
patent: 4452646 (1984-06-01), Zuleeg
patent: H390 (1987-12-01), Lee et al.
patent: 4738934 (1988-04-01), Johnston et al.
patent: 4783688 (1988-11-01), Shannon
patent: 4803526 (1989-02-01), Terada et al.
patent: 4843441 (1989-06-01), Willard
patent: 4855246 (1989-08-01), Codella et al.
patent: 4963501 (1990-10-01), Ryan et al.
patent: 5002897 (1991-03-01), Lewis et al.
patent: 5187379 (1993-02-01), Noda
patent: 5196358 (1993-03-01), Boos
patent: 5367180 (1994-11-01), Asai et al.
patent: 5376812 (1994-12-01), Oku
patent: 5532507 (1996-07-01), Wada
patent: 5536666 (1996-07-01), Miller et al.
patent: 5565696 (1996-10-01), Miller et al.
patent: 5578512 (1996-11-01), Tao
patent: 5688703 (1997-11-01), Klingbeil et al.
patent: 5804849 (1998-09-01), Wennekers
patent: 5907168 (1999-05-01), Childs
patent: 6005267 (1999-12-01), Griffin et al.
patent: 6114195 (2000-09-01), Nishihori et al.
patent: 6134424 (2000-10-01), Nishihori et al.
patent: 6236070 (2001-05-01), Griffin et al.
patent: 6359324 (2002-03-01), Tichauer
patent: 6458640 (2002-10-01), Li
patent: 6541319 (2003-04-01), Mun et al.
patent: 6559513 (2003-05-01), Miller et al.
patent: 6583470 (2003-06-01), Maki et al.
patent: 6620688 (2003-09-01), Woo et al.
patent: 6673645 (2004-01-01), Heineke et al.
patent: 2003/0017660 (2003-01-01), Li
patent: 2003/0132463 (2003-07-01), Miyoshi
patent: 2005/0062069 (2005-03-01), Saito et al.
patent: 2006/0220154 (2006-10-01), Gajadharsing et al.
patent: 2007/0138515 (2007-06-01), Winslow
patent: 1 806 779 (2007-07-01), None
patent: 61-18180 (1986-01-01), None
patent: 2007-184617 (2007-07-01), None
Goud et al., Two-Dimensional Analysis and Design Considerations of High-Voltage Planar Junctions Equipped with Field Plate and Guard Ring, IEEE Transactions on Electron Devices, vol. 38, No. 6, Jun. 1991; pp. 1497-1504.
Jaume et al., High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers, IEEE Transactions on Electron Devices, vol. 38, No. 7, Jul. 1991; pp. 1681-1684.
Feiler et al., Multistep Field Plates for High-Voltage Planar p-n Junctions, IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992; pp. 1514-1520.
Goud et al., Breakdown Voltage of Field Plate and Field-Limiting Ring Techniques; Numerical Comparison, IEEE Transactions on Electron Devices, vol. 39, No. 7, Jul. 1992; pp. 1768-1770.
Mok et al., A Novel High-Voltage High-Speed MESFET Using a Standard GaAs Digital IC Process, IEEE Transactions on Electron Devices, vol. 41, No. 2, Feb. 1994; pp. 246-250.
Goud et al., Analysis and Optimal Design of Semi-Insulator Passivated High-Voltage Field Plate Structures and Comparison with Dielectric Passivated Structures, IEEE Transactions on Electron Devices, vol. 41, No. 10; Oct. 1994, pp. 1856-1865.
Murray et al., Optimization of Interconnected-Induced Breakdown Voltage in Junction Isolated IC's Using Biased Polysilicon Field Plates, IEEE Transactions on Electron Devices, vol. 44, No. 1, Jan. 1997; pp. 185-189.
Asano et al., Novel High Power AlGaAs/GaAs HFET with a Field-Modulating Plate Operated at 35V Drain Voltage, IEDM 98, pp. 59-62; 1998.
Wada et al., An 0.1-um Voidless Double-Deck-Shaped (DDS) Gate HJFET with Reduced Gate-Fringing-Capacitance, IEEE Transactions on Electron Devices, vol. 46, No. 5, May 1999; pp. 859-864.
Matsunaga et al., A Low-Distortion 230W GaAs Power FP-HFET Operated at 22V for Cellular Base Station, IEDM 2000, pp. 393-396.
Karmalker et al., Enhancement of Breakdown Voltage in A1GaN/GaN High Electron Mobility Transistors Using a Field Plate, IEEE Transactions on Electron Devices, vol. 48, No. 8, Aug. 2001; pp. 1515-1521.
Karmalker et al., Resurf A1GaN/GaN HEMT for High Voltage Power Switching, IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001; pp. 373-375.
Tarplee et al., Design Rules for Field Plate Edge Termination in SiC Schottky Diodes, IEEE Transactions on Electron Devices, vol. 48, No. 12, Dec. 2001; pp. 2659-2664.
Ando et al., 10-W/mm A1GaN-GaN HFET With a Field Modulating Plate, IEEE Electron Devices Letters, vol. 24, No. 5, May 2003; pp. 289-291.
Ando et al., 12 W/mm Recessed-Gate A1GaN/GaN Heterojunction Field-Plate FET, IEDM 2003, pp. 563-566.
Wakejima et al., A GaAs-Based Field-Modulating Plate HFET with Improved WCHMA Peak-Output-Power Characteristics, IEEE Transactions on Electron Devices, vol. 50, No. 9, Sep. 3; pp. 1983-1987.
Okamoto et al., High-Power Recessed-Gate A1GaN-GaN HFET With a Field-Modulating Plate, IEEE Transactions on Electron Devices, 2004 IEEE; pp. 1-6.
Wu et al., 30-W/mm GaN HEMTs by Field Plate Optimization, IEEE Electron Device Letters, vol. 25, No. 3, Mar. 2004; pp. 117-119.
Okamoto et al., Improved Power Performance for a Recessed-Gate A1GaN-GaN Heterojunction FET With a Field-Modulating Plate, IEEE Transactions on Microwave Theory and Techniques; vol. 52, No. 11; pp. 2536-2540.
Xing et al., High Breakdown Voltage A1GaN-GaN HEMTs Achieved by Multiple Field Plates, IEEE Electron Device Letters, vol. 25, No. 4, Apr. 2004, pp. 161-163.
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