Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-12-31
2002-11-19
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C438S163000
Reexamination Certificate
active
06482685
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for fabricating a thin film transistor and more particularly, relates to a method for fabricating a low temperature polysilicon thin film transistor that incorporates a multi-layer channel passivation step.
BACKGROUND OF THE INVENTION
In recent years, large liquid crystal cells have been used in flat panel displays. The liquid crystal cells are normally constructed by two glass plates joined together with a layer of a liquid crystal material sandwiched in-between. The glass substrates have conductive films coated thereon with at least one of the substrates being transparent. The substrates are connected to a source of power to change the orientation of the liquid crystal material. A possible source of power is a thin film transistor that is used to separately address areas of the liquid crystal cells at very fast rates. The TFT driven liquid crystal cells can be advantageously used in active matrix displays such as for television and computer monitors.
As the requirements for resolution of liquid crystal monitors increase, it becomes desirable to address a large number of separate areas of a liquid crystal cell, called pixels. For instance, in a modern display panel, more than 3,000,000 pixels may be present. At least the same number of transistors must therefore be formed on the glass plates so that each pixel can be separately addressed and left in the switched state while other pixels are addressed.
Thin film transistors are frequently made with either a polysilicon material or an amorphous silicon material. For TFT structures that are made of amorphous silicon material, a common structure is the inverted staggered type which can be back channel etched or tri-layered. The performance of a TFT and its manufacturing yield or throughput depend on the structure of the transistor. For instance, the inverted staggered back channel etched TFT can be fabricated with a minimum number of six masks, whereas other types of inverted staggered TFT require a minimum number of nine masks. The specification for a typical inverted staggered back channel etched TFT includes an amorphous silicon that has a thickness of 3,000 Å, a gate insulator of silicon nitride or silicon oxide, a gate line of Mo/Ta, a signal line of Al/Mo and a storage capacitor. The requirement of a thick amorphous silicon layer in the TFT device is a drawback for achieving a high yield fabrication process since deposition of amorphous silicon is a slow process. A major benefit for the amorphous silicon TFT is its low leakage current which enables a pixel to maintain its voltage. On the other hand, an amorphous silicon TFT has the drawback of a low charge current (or on current) which requires an excessive amount of time for a pixel to be charged to its required voltage.
FIG. 1
shows an enlarged, cross-sectional view of a conventional amorphous silicon TFT structure. Amorphous TFT
10
is built on a low cost glass substrate
12
. On top of the glass substrate
12
, a gate electrode
14
is first deposited of a refractory metal such as Cr, Al or Al alloy and then formed. A gate insulating layer
16
is normally formed in an oxidation process. For instance, a high density TaO
x
on a Ta gate can be formed to reduce defects such as pin holes and to improve yield. Another gate insulating layer
20
is then deposited of either silicon oxide or silicon nitride. An intrinsic amorphous silicon layer
22
is then deposited with a n
+
doped amorphous silicon layer
24
deposited on top to improve its conductivity. Prior to the deposition of the doped amorphous silicon layer
24
, an etch stop
26
is first deposited and formed to avoid damages to the amorphous silicon layer
22
in a subsequent etch process for a contact hole. The doped amorphous silicon layer
24
is formed by first depositing the amorphous silicon layer in a chemical vapor deposition process and then implanting ions in an ion implantation process. Boron ions are normally used to achieve n
+
polarity. A drain region
30
and a source region
32
are then deposited and formed with a pixel electrode layer
34
of ITO (indium-tin-oxide) material deposited and formed on top. The drain region
30
and the source region
32
are normally deposited of a conductive metal layer. A suitable conductive metal may be a bilayer of Cr/Al. The structure is then passivated with a passivation layer
36
.
A second conventional inverted staggered type TFT
40
is shown in FIG.
2
. The TFT
40
is frequently called the back channel etched type inverted staggered TFT. A gate electrode
42
is first formed on a non-conducting glass substrate
38
. The gate electrode
42
is connected to a gate line (not shown) laid out in the row direction. A dielectric material layer
44
of either silicon oxide or silicon nitride is used to insulate the gate electrode
42
. After an amorphous silicon layer
46
and a contact layer
48
are sequentially deposited, patterned and etched, source electrode
50
and drain electrode
52
are formed to provide a channel
54
in-between the two electrodes, hence the name back channel etched TFT. The source electrode
50
of each TFT is connected to a transparent pixel electrode
56
independently formed in the area surrounded by the gate lines and the drain lines (not shown). A transparent passivation layer
58
of a material such as silicon nitride is deposited on the completed structure.
As shown in
FIG. 2
, the gate electrode
42
is frequently formed of chromium or other similar metals on the transparent glass substrate
38
. The dielectric layer
44
of gate oxide or silicon nitride is formed to insulate the upper surface of the glass substrate
38
including the top surface of the gate electrode
42
. A semi-conducting layer
46
, which may be formed of amorphous silicon is stacked on the dielectric film
44
over the gate electrode
42
. The drain electrode
52
and the source electrode
50
are formed on the semi-conducting film
46
and are separated from each other by a predetermined distance forming the channel section
54
. The two electrodes each has a contact layer of
48
and a metal layer which are electrically connected to the semi-conducting layer
46
. The transparent electrode
44
may be formed of ITO.
A second type of TFT is made by using a polysilicon material. Polysilicon is more frequently used for displays that are designed in a smaller size, for instance, up to three inch diagonal for a projection device. At such a small size, it is economical to fabricate the display device on a quartz substrate. Unfortunately, large area display devices cannot be made on quartz substrates. The desirable high performance of polysilicon can be realized only if a low temperature process can be developed to enable the use of non-quartz substrates. For instance, in a recently developed process, large area polysilicon TFT can be manufactured at processing temperatures of less than 600° C. In the process, self-aligned transistors are made by depositing polysilicon and gate oxide followed by source/drain regions which are self-aligned to the gate electrode. The device is then completed with a thick oxide layer, an ITO layer and aluminum contacts.
Polysilicon TFTs have the advantage of a high charge current (or on current) and the drawback of a high leakage current. It is difficult to maintain the voltage in a pixel until the next charge in a polysilicon TFT due to its high leakage current. Polysilicon also allows the formation of CMOS devices, which cannot be formed by amorphous silicon. For the fabrication of larger displays, a higher mobility may be achieved by reducing the trap density around the grain boundaries in a hydrogenation process.
When compared to the amorphous silicon thin film transistors, the low temperature polysilicon TFTs have higher mobility and higher drive current. However, due to the fabrication technology and the structure of the polysilicon element, the activation process (or the annealing process) for the dopant ions in the source area
Chen Chih-Chiang
Lin Kun-Chih
Chaudhuri Olik
Industrial Technology Research Institute
Schillinger Laura M
Tung & Associates
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