Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-11-15
2001-08-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S591000, C438S592000, C438S593000, C438S647000, C438S649000, C438S643000, C438S653000, C438S655000, C438S657000, C438S644000
Reexamination Certificate
active
06277719
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a low resistance poly-Si/metal gate structure for MOS applications.
2) Description of the Prior Art
As MOS dimensions are reduced, the contact resistance and sheet resistance increase. In conventional gate electrodes using polysilicon/silicide, such as Poly-Si/WSi
x
, the increased resistance causes a large gate RC delay, thereby degrading performance. This is particularly detrimental in high speed memory chip and logic device applications.
One approach to overcoming the problems caused by high gate resistance in Poly-Si/silicide gate electrodes is disclosed by Sitaram (5,384,285). Resistance in a Poly-Si/Silicide gate electrode can be reduced by preventing detrimental transition-metal reactions during processing, particularly with oxygen. Sitaram prevents reactions with the transition-metal layer by forming a boron nitride or boron oxynitride capping layer over the transition metal layer. The capping layer is removed after formation of the silicide. While this approach lowers the sheet resistance of the silicide layer, it does not achieve the low contact resistance or overall gate electrode resistance of the composite poly-Si/tungsten gate electrode of the present invention. Nor does it provide the thermal stability of the present invention.
Similarly, Apte et al. (5,593,924) disclose the use of a removable capping layer composed of a metal such as titanium nitride to reduce contamination in a silicide layer; thereby lowering sheet resistance. Again, this invention does not address the other problems associated with Poly-Si/silicide gate electrodes described previously.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,384,285 (Sitaram et al.) and U.S. Pat. No. 5,593,924 (Apte) described above, as well as, the following US Patents.
U.S. Pat. No. 5,103,272 (Nishiyama) shows a process for forming titanium silicide contacts on a polysilicon gate and source and drain regions using a titanium nitride barrier layer to prevent the titanium silicide layer from agglomerating.
U.S. Pat. No. 5,550,079 (Lin) shows a silicide shunt with a tungsten nitride barrier layer.
U.S. Pat. No. 5,668,065 (Lin) shows a polysilicon/tungsten silicide/silicon nitride gate structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a gate for MOS applications which minimizes RC delay by reducing the sheet resistance and contact resistivity of the gate.
It is another object of the present invention to fabricate a composite metal/polysilicon gate structure having good thermal stability over a wide temperature range.
It is another object of the present invention to provide a method for forming a diffusion barrier layer over a polysilicon layer that is not susceptible to peeling.
It is yet another object of the present invention to provide an economical and robust process for manufacturing a low resistance metal/polysilicon gate for use in MOS devices.
To accomplish the above objectives, the present invention provides a method for fabricating a composite metal/polysilicon gate with (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. The process begins by forming a first insulating layer over a silicon substrate. A polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer. The capping layer, the tungsten layer, the diffusion barrier layer, and the first insulating layer are patterned, thereby defining a gate structure. The basic steps in the present invention are shown in Table 1.
TABLE 1
FIRST EMBODIMENT
SECOND EMBODIMENT
oxide deposition
oxide deposition
polysilicon deposition
polysilicon deposition
anneal (anti-peeling)
anneal (anti-peeling)
titanium deposition
titanium nitride deposition
anneal to form TiSi
x
tungsten deposition
titanium nitride deposition
gate patterning
tungsten deposition
gate patterning
The present invention provides considerable improvement over the prior art in terms of sheet resistance and contact resistivity, and consequently in terms of RC delay, allowing faster devices. While conventional gates have a sheet resistance of about 2.5 Ohm/□ and a contact resistivity of about 1E-3 Ohm·cm
2
, a gate fabricated according to the present invention provides a sheet resistance of about 1.6 Ohm/□ and a contact resistivity of about 2E-7 Ohm·cm
2
.
Also, a gate formed according to the present invention has been demonstrated to have a lower susceptibility to peeling of the diffusion barrier layer, and improved thermal stability compared to conventional gates.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4561907 (1985-12-01), Raicu
patent: 5103272 (1992-04-01), Nishiyama
patent: 5350698 (1994-09-01), Huang et al.
patent: 5384285 (1995-01-01), Sitaram et al.
patent: 5441904 (1995-08-01), Kim et al.
patent: 5550079 (1996-08-01), Lin
patent: 5593924 (1997-01-01), Apte et al.
patent: 5668065 (1997-09-01), Lin
patent: 6017808 (2000-01-01), Wang et al.
patent: 6147388 (2000-11-01), Ma et al.
patent: 6198144 (2001-03-01), Pan et al.
Chang Randy (C. H.)
Chern Jin-Dong
Liaw Ing-Ruey
Tsai Kwong-Jr
Ackerman Stephen B.
Niebling John F.
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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