Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
1999-01-25
2001-04-10
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S592000, C257S411000
Reexamination Certificate
active
06214705
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87120800, filed Dec. 15, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET), and more particularly, to a manufacturing method of multi-layered gate electrode on a MOSFET.
2. Description of Related Art
As semiconductor devices are highly integrated, the gate electrode of a MOSFET becomes narrower. If the gate electrode is decreased in width, its electric resistance is increased, thereby lowering the operating speed of the semiconductor device.
A phosphorus-doped polysilicon layer is formed as a gate electrode with an aim of reducing the resistance of the gate electrode. The phosphorous atoms in the polysilicon layer are doped to lower the resistance of the gate electrode. The phosphorus-doped polysilicon layer is formed in a process comprising an annealing step for uniformly distributing the phosphorus atoms in it. For achieving the distribution, the annealing step should be performed at a high temperature. However, in this high temperature annealing, the phosphorus atoms often accumulate in a great numbers near the interface between the polysilicon layer and the gate dielectric located beneath the polysilicon layer. Since the thickness of the gate dielectric is desirably reduced, some of the accumulated phosphorus atoms can penetrate through the gate dielectric layer to the channel region beneath the gate dielectric, thereby undesirably lowering the gate breakdown voltage.
A phosphorus-doped amorphous silicon layer is proposed for use in gate formation to reduce the accumulation phenomenon of the phosphorus atoms. However, the phosphorus atoms do not distribute uniformly to satisfy requirements, and thereby cause an undesirable raise in the gate resistance.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a manufacturing method for a gate electrode on a MOSFET to reduce the accumulation phenomenon encountered in the prior art.
In another aspect, the present invention provides a manufacturing method for a gate electrode that lowers the gate resistance.
In accordance with the present invention, the manufacturing method of a gate electrode comprises the steps of forming an undoped amorphous silicon layer on a substrate and forming a doped amorphous silicon layer on the undoped amorphous silicon layer.
In accordance with one particular embodiment of the present invention, the method for manufacturing a gate electrode comprises the steps of alternately forming a plurality of undoped amorphous silicon layers and a plurality of doped amorphous silicon layers on a gate dielectric, and annealing the doped and the undoped amorphous silicon layers.
The amorphous silicon layers formed in an alternating manner of the gate electrode manufacturing by the present method can unify their impurity distribution, thereby lowering the resistance of the gate electrode. Furthermore, the interfaces between the formed amorphous silicon layers with different doping status limit the diffusion paths of the impurities, thereby reducing their chances to accumulate near the gate dielectric during the annealing step.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4666816 (1987-05-01), Kojima
patent: 4679062 (1987-07-01), Okamoto
patent: 5663085 (1997-09-01), Tanigawa
patent: 5885889 (1999-03-01), Aisou
Blum David S
Bowers Charles
Huang Jiawei
J.C. Patents
United Microelectronics Corp.
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