Method for fabricating a four fin capacitor structure

Details Method for fabricating a four fin capacitor structure Method for fabricating a four fin capacitor structure

1996-06-18

1998-02-24

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 47, 437 52, 437919, 148DIG14, H01L 2170

Patent

active

057211540

ABSTRACT:
A unique DRAM structure has increased capacitance by using a four parallel fin capacitor structure. A preferred method for fabricating the DRAM is disclosed. DRAM cell is formed on a silicon substrate having a first conductivity type. Field oxide (FOX) regions are defined in the substrate to separate DRAM cells. Drain and source regions are formed in the substrate by forming in the substrate regions. On the substrate surface and between the drain and source, a gate region is formed. The gate region comprises a gate oxide, a Poly-1 layer, a tungsten silicide (WSi) layer, an oxide layer, and a SiO.sub.2 or SiN layer. SiO.sub.2 or SiN spacers cover the sides of the gate regions. Above the gate region is an insulating layer of TEOS (tetraethylorthosilicate) or BPSG (borophosphosilicate). A Poly-2 layer having a second conductivity type opposite the first conductivity type contacts the source and drain regions. The Poly-2 layer forms a bitline where it contacts the source region. Layers of WSi, thermal oxide or thin TEOS, and Si.sub.y N.sub.x, such as Si.sub.3 N.sub.4, cover the bitline. The sides of the bitline are covered with Si.sub.y N.sub.x spacers. A four parallel fin capacitor contacts the Poly-2 layer contacting the drain region. The capacitor comprises a Poly-3.1 layer and a Poly 3.2 layer both doped to the second conductivity type, a thin dielectric layer, such as nitride film/oxide film (NO) or oxide film
itride film/oxide film (ONO), and a Poly-4 layer doped to the second conductivity type.

REFERENCES:
patent: 5364809 (1994-11-01), Kwon et al.
patent: 5492850 (1996-02-01), Ryou
patent: 5508222 (1996-04-01), Sakao
patent: 5550076 (1996-08-01), Chen

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