Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-09-20
2002-04-23
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S250000, C438S258000, C438S643000
Reexamination Certificate
active
06376325
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 1999-40768, filed on Sep. 21, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of a semiconductor device, and more particularly to a method for fabricating a ferroelectric device.
2. Background of the Invention
Modern data processing systems require that a substantial portion of the information stored in its memory be randomly accessible to ensure rapid access to the information. Because high speed operation is required of semiconductor memories, ferroelectric random access memories (FRAMs) have been researched and developed. Such FRAMs are nonvolatile memories with a ferroelectric capacitor including a pair of capacitor electrodes with a ferroelectric material between them. The ferroelectric material has two different stable polarization states that can be defined with a hysteresis loop depicted by plotting the polarization against applied voltage.
FRAMs are nonvolatile like flash memories and have many advantages. For example, they are programmable with a low voltage, e.g., less than 5 V (for flash memory, 18 to 22V is required), and have less than 40 nsec access time (for flash memory, microseconds are required). Also FRAMs are known for their durability, i.e., virtually unlimited numbers of read and write cycles, more than 1E12 cycles (for flash memory, only about 1E5 to 1E6 cycles are possible). FRAMs also consume low power and exhibit radiation hardness.
Conventionally, for the fabrication of FRAMs, a post-deposition annealing process is carried out on as-deposited ferroelectric material to allow a crystalline phase, i.e., a perovskite ferroelectric dielectric phase, which has the required ferroelectric dielectric characteristics. Typically ferroelectric materials are subjected to a heat treatment in excess of 550° C. for necessary crystallization. Also, the integration process requires an annealing step in an oxygen ambient. During these annealing processes at high temperatures or in an oxygen ambient, a thin insulating layer of oxide is formed at the interface between the lower electrode of a ferroelectric capacitor and the contact plug of a polysilicon. Polysilicon plugs are widely used for interconnection between capacitor lower electrodes and the junction regions of the access transistors because a contact plug structure is suitable for the recent trend toward high degree of integration of integrated circuits. Such an oxide insulating layer causes poor contact characteristic therebetween (i.e., increasing contact resistance). During these annealing processes, oxygen is introduced into the interface through two diffusion paths, one diffusion path along the sidewall of the lower electrode and the other diffusion path along the top surface of the lower electrode.
FIG.
1
and
FIG. 2
are cross-sectional views of a semiconductor substrate schematically showing a ferroelectric capacitor according to U.S. Pat. No. 5,854,104 entitled “PROCESS FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A FERROELECTRIC CAPACITOR” and U.S. Pat. No. 5,489,548 entitled “METHOD OF FORMING HIGH-DIELECTRIC CONSTANT MATERIAL ELECTRODES COMPRISING SIDEWALL SPACES”, the disclosure of which are incorporated herein by reference.
In
FIG. 1
, reference number
8
denotes a diffusion barrier layer of TiO
2
, reference number
12
and
13
denote a lower electrode of a TiN and Pt respectively. Reference number
14
denotes a PZT film. According to the prior art of
FIG. 1
, the formation of the lower electrode patterns
12
and
13
is followed by PZT deposition and post-deposition annealing at high temperature. Also, after depositing the diffusion barrier layer
8
, high temperature annealing above 500° C. in oxygen ambient is performed to improve barrier characteristics. Such high temperature annealing processes cause oxidation at the interface between TiN film
12
and the contact plug
11
. The oxidation is caused by the diffusion of oxygen through the sidewall of the stacked ferroelectric capacitor. Oxygen also penetrates the platinum
13
easily to oxidize underlying TiN layer
12
thereby making the TiN layer
12
less conductive.
In
FIG. 2
, reference number
34
denotes a polysilicon contact plug, reference number
32
denotes an insulating layer (SiO
2
), reference number
36
denotes an adhesion layer of TiN, reference number
40
denotes a sidewall oxidation barrier layer of SiO
2
, reference number
42
denotes a lower electrode of a platinum electrode and reference number
44
denotes a high dielectric BST film. The high dielectric capacitor shown in
FIG. 2
has a sidewall spacer
40
, so that it can prevent oxidation of the TiN adhesion layer
36
at the lateral surface unlike the structure as shown in FIG.
1
. However, there still remain some problems with this structure. For example, as described above, oxygen can diffuse through the platinum
42
easily into the underlying TiN layer
36
to oxidize the upper surface thereof. Also, the platinum electrode
42
does not normally adhere to the SiO
2
insulating layer
32
, causing a so-called “lifting phenomenon.”
As described above, the platinum is widely used as a lower electrode in ferroelectric film application since it is nonreactive to the ferroelectric film. The lower electrode layer is relatively thick and is a multi-layer structure to ensure anti-oxidation barrier for the contact plug. However, as the semiconductor device highly integrates, it becomes more and more difficult to etch such a thick lower electrode layer to form a lower electrode pattern. Particularly, a photoresist layer is relatively thin in high integration integrated circuit process to ensure accurate pattern formation. Accordingly, a photoresist layer can be etched completely during a photo-etching process. This damages the underlying ferroelectric capacitor, and degrades ferroelectric characteristics of the ferroelectric capacitor.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a reliable ferroelectric capacitor overcoming the problems described above and method for fabricating the same.
In the present invention, a capacitor lower electrode is preferably formed of stacked patterns. An oxidation barrier layer is formed on sidewalls of a portion of the lower electrode. After that, the remainder of the lower electrode is formed. As a result, overall height of the electrode layers (lower electrode layer and upper electrode layer) and the ferroelectric layer that are to be etched after formation of the oxidation barrier layer is reduced. This minimizes consumption of the photoresist layer. In addition, the possibility of etching the electrode layer under the photoresist layer can be reduced.
More particularly, the lower electrode is made of a multi-layer structure having first and second lower electrode patterns. For this, the first lower electrode layer is formed on an interlayer-insulating layer that has a contact plug therein. After the first lower electrode layer is patterned to be electrically connected to the contact plug, the oxidation barrier layer is formed on sidewalls of the first lower electrode pattern to prevent oxidation thereof. Then, a second lower electrode layer, a ferroelectric layer and an upper electrode layer are sequentially formed. Using a photo-etching process, the upper electrode, ferroelectric and second lower electrode layers are etched and patterned to form a ferroelectric capacitor. The second lower electrode pattern extends outward from the outer edges of the first lower electrode pattern.
The oxidation barrier layer is preferably made of an insulating layer such as SiO
2
and Si
3
N
4
. The sidewall oxidation barrier layer is preferably formed by the steps of depositing an oxidation barrier material on the first lower electrode pattern and isotropically etching the oxidation barrier material to form the oxidation barrier layer on sidewalls of the first lower electro
Lebentritt Michael S.
Luu Pho
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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