Method for fabricating a dual-gate metal-semiconductor field eff

Details Method for fabricating a dual-gate metal-semiconductor field eff Method for fabricating a dual-gate metal-semiconductor field eff

1993-03-29

1994-09-27

Thomas, Tom

Fishing, trapping, and vermin destroying

437 56, 437 65, 437176, 437912, 148DIG73, H01L 21265

Patent

active

053507029

ABSTRACT:
A dual gate metal semiconductor field effect transistor is disclosed which comprises a semi-insulating compound semiconductor substrate, a first and a second insulating layer in stripe pattern in different width formed on said semiconductor substrate at a predetermined angle against the <110> direction, a first semiconductor layer having a first and a second voids on said first and second insulating layers in stripe pattern, a second semiconductor layer subsequently formed to said first semiconductor layer, source and drain regions having impurities partially diffused to said first and second semiconductor layers, a first and a second gate electrodes formed in different width on said second semiconductor layer positioned corresponding to said first and second insulating layers in stripe pattern, source and drain electrodes formed on said source and drain regions. With such a construction, by forming the void at the lower part of the conductive layer by using the selective MOCVD according to the crystal orientation of the substrate, the conductive thickness can be adjusted, so that recess etching is not required therefor. In addition, leakage current can be prevented without forming the buffer layer of high purity requiring a high resistance as in the conventional technique for the semiconductor substrate and conductive layer, and properties of low noise and high gain is obtained.

REFERENCES:
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patent: 4601096 (1986-07-01), Calviello
patent: 4639275 (1987-01-01), Holoyak, Jr.
patent: 4791072 (1988-12-01), Kiehl
patent: 4883770 (1989-11-01), Dohler et al.
patent: 5164218 (1992-11-01), Tsuruta et al.

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