Method for fabricating a DRAM memory cell arrangement having...

Details Method for fabricating a DRAM memory cell arrangement having... Method for fabricating a DRAM memory cell arrangement having...

2007-12-25

2007-12-25

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

11169812

ABSTRACT:
The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The FinFETs and CFETs are formed in a manner oriented to semiconductor fins arranged in cell rows. Within the cell rows, the semiconductor fins are spaced apart from one another by cell insulator structures. Adjacent cell rows are spaced apart from one another by striplike trench insulator structures. The semiconductor fins are in each case recessed in one or in two inner trench sections by means of gate trenches which extend from a longitudinal side of the respective semiconductor fin to the opposite longitudinal side. By isotropically etching the oxide of the trench insulator structures, pockets (fin trenches) are formed, in a self-aligned manner with respect to the gate trenches in the trench insulator structures and filled with a gate conductor material. Vertical gate electrode sections emerge without etching back from the deposited gate conductor material. In conjunction with trench capacitors as cell insulator structures, an improved decoupling and insulation of the trench capacitors from word lines led above the trench capacitors are achieved.

REFERENCES:
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4811067 (1989-03-01), Fitzgerald et al.
patent: 6255683 (2001-07-01), Radens et al.
patent: 6437388 (2002-08-01), Radens et al.
patent: 103 61 695 (2003-12-01), None
patent: 1 017 095 (2000-07-01), None

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