Method for fabricating a DRAM cell capacitor

Details Method for fabricating a DRAM cell capacitor Method for fabricating a DRAM cell capacitor

1999-03-30

2000-12-12

Utech, Benjamin L.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438399, 438694, H01L 2120

Patent

active

061598208

ABSTRACT:
Disclosed is an improved method for fabricating a DRAM cell capacitor which can provide a self aligned contact hole to a storage node of a capacitor and can increase capacitor surface areas by way of merging the contact hole forming step and the storage node forming step. The merging technique provides reduced photolithography process and thereby reduces processing cost. The method includes the steps of forming a first insulating layer over a semiconductor substrate having a plurality of gate electrode structures and a plurality of contact pads which is disposed between adjacent the gate electrode structures, the first insulating layer having a plurality of bit line structures therein; sequentially forming a first material layer, a second insulating layer, and a second material layer over the first insulating layer; forming a negative-type photoresist pattern over the second material layer; sequentially etching the second material layer, the second insulating layer, and the first material layer using the photoresist pattern as a mask and thereby forming a plurality of first openings; removing the photoresist pattern; forming a plurality of sidewalls spacers made of a first conductive material layer on the lateral edges of the first openings, the conductive sidewalls spacers having etch selectivity with respect to the first insulating layer; etching the first insulating layer between adjacent the plurality of the conductive sidewalls spacers and thereby forming self aligned a plurality of second openings to the contact pad; filling up the first openings and the second openings with a second conductive material layer; planarizing until a top surface of the second insulating layer is exposed; and etching the exposed second insulating layer using the first material layer as an etch stopper and thereby forming a plurality of storage nodes to the contact pads.

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