Method for fabricating a doped polysilicon feature in a semicond

Details Method for fabricating a doped polysilicon feature in a semicond Method for fabricating a doped polysilicon feature in a semicond

1998-08-14

2000-08-22

Chaudhari, Chandra

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

438264, 438923, H01L 21425

Patent

active

061071692

ABSTRACT:
In a non-volatile semiconductor memory device, a top surface of a floating gate that is made of polysilicon is advantageously kept smooth to increase the uniformity of an overlying interpoly dielectric layer onto which a control gate is formed. The floating gate is doped after at least a portion of the overlying interpoly dielectric layer has been formed. Ion implantation techniques are employed to implant dopants through the overlying layer or layers and into the floating gate. Consequently, the potential for polysilicon grain growth at or near the top surface of the floating gate, which can lead to significant depressions in the overlying layers and data retention problems in the memory cell, is substantially reduced.

REFERENCES:
patent: 4669176 (1987-06-01), Kato
patent: 4769340 (1988-09-01), Chang et al.
patent: 5147813 (1992-09-01), Woo
Wolf, Silicon Processing for the VLSI Era, vol. 1: Process Technology, pp. 294-295, 321-325, 1986.

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