Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-20
2004-05-18
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S753000, C257S763000
Reexamination Certificate
active
06737692
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of components, in particular microelectronic components and specifically in the field of semiconductor memories.
During the fabrication of components, layers of different materials are successively applied and patterned. In order to ensure the reliability of the fabricated components, the applied layers must have a sufficient adhesion. What is problematic is e.g. the adhesion of insulation materials, e.g. silicon oxide and silicon nitride, on noble metals and other metals that are difficult to oxidize, in particular those from subgroup VIIIb of the periodic table.
Platinum or iridium is used e.g. in the fabrication of the capacitor electrodes of semiconductor memories with a ferroelectric or high-∈-dielectric (∈ generally greater than 20) capacitor dielectric, since this metal is sufficiently resistant to the process conditions required for the deposition of the capacitor dielectric. In particular, the electrodes have to withstand an oxidation at elevated temperatures. However, the pronounced chemical inertness is more of a disadvantage with regard to the adhesion to the standard insulation material used in semiconductor technology. It is presumed that a good adhesion between two layers is connected with a certain chemical interaction or interdiffusion of the adjacent layers. By way of example, a TiAl
3
layer forms between titanium and aluminum, and has a favorable effect on the adhesion. Formation of a metal oxide layer in a manner beneficial to adhesion is also observed when depositing metals that are relatively easy to oxidize onto silicon oxide.
In the case of the noble metals or other metals that are difficult to oxidize, there is very little chemical interaction with e.g. oxide layers. Therefore, problems with the adhesion occur particularly frequently in this case. This is critical particularly in the case of increasingly smaller structures, as are found e.g. in semiconductor memories. In that case, the electrodes are formed e.g. by deposition onto a prepatterned insulation layer with subsequent polishing-back (CMP=chemical mechanical polishing). The rotating grinding wheel used for the polishing-back in this case exerts a certain mechanical pressure on the deposited metal layer, which pressure, for lack of adhesion, can lead to a stripping away of the metal layer. Furthermore, cleaning steps after possible etching patterning of the metal layer or during the ultrasonic bonding of finished processed semiconductor chips have also been found to be a particular mechanical burden.
In order to improve the adhesion of noble metals, for example of a storage capacitor of a semiconductor memory, U.S. Pat. No. 5,668,040, teaches providing a layer of a transition metal, e.g. from subgroup IVb, Vb or VIb, between the noble metal of the bottom capacitor electrode and the insulation layer including silicon oxide. This transition metal forms a metal nitride layer at the interface with the noble metal layer during a thermal treatment in an ammonia-containing atmosphere. In this case, the noble metal layer does not react with nitrogen or the transition metal. Furthermore, a metal oxide layer forms at the interface between the transition metal and silicon oxide. What is problematic with this approach, however, is that the etched edges of the transition metal comes into contact with the capacitor dielectric that is subsequently applied, and is oxidized at least there. Moreover, transition metal can diffuse into the capacitor dielectric and impair the dielectric or ferroelectric properties thereof.
In order to avoid the diffusion of a transition metal into the capacitor dielectric, it is possible, as proposed e.g. in Published European Patent Application EP 0 697 718 A1, for the deposition of the capacitor dielectric to be preceded by an oxidation of the edges of the transition metal, in the case of which, however, a considerable increase in volume is observed which can lead to a mechanical fracture of the noble metal layer seated on the transition metal layer. Moreover, the cross section available for the contact connection of the bottom electrode is restricted.
Published German Patent Application DE 198 28 969 A1 describes a method for fabricating a semiconductor component in which a silicon layer is deposited as an adhesion promoter between a top metal electrode of a storage capacitor and an oxide layer.
Issued German Patent DE 196 01 592 C1 discloses, for the purpose of improving the adhesion of a platinum layer on a dielectric carrier layer of a sensor, providing a platinum silicide layer between the dielectric carrier layer and the platinum layer. The platinum silicide layer is fabricated by siliconizing a silicon layer applied before the deposition of the platinum layer.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a component, which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the invention to provide a method for fabricating a component with an improved adhesion of a noble metal layer to an insulation layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a component including steps of: applying a noble metal layer to a substrate and subsequently applying a silicon layer to the substrate such that a surface of the noble metal layer contacts the silicon layer; performing a siliconization such that the surface of the noble metal layer contacting the silicon layer is siliconized; performing an oxidation to oxidize a silicide layer formed from the silicon layer; and applying an insulation layer.
In accordance with an added feature of the invention, when performing the oxidation step, unsiliconized regions of the silicon layer that may have remained are oxidized.
In accordance with an additional feature of the invention, the siliconization step is effected in situ while performing the step of applying the silicon layer.
In accordance with another feature of the invention, the method includes patterning the noble metal layer before performing the step of applying the silicon layer.
In accordance with a further feature of the invention, the method includes: performing the step of applying the noble metal layer by applying the noble metal layer to a ferroelectric or dielectric capacitor dielectric covering a further noble metal layer; forming a stack by patterning the further noble metal layer, the capacitor dielectric, and the noble metal layer using a common mask; and conformally depositing the silicon layer onto the stack, and siliconizing and oxidizing the silicon layer such that the silicon layer is completely oxidized in a region directly contacting the capacitor dielectric.
In accordance with a further added feature of the invention, the step of applying the insulation layer is performed after the step of performing the oxidation.
In accordance with a further additional feature of the invention, the method includes: before performing the oxidation, patterning the noble metal layer and the silicon layer by using a lithographically fabricated mask.
In accordance with yet an added feature of the invention, the method includes: introducing at least one contact hole into the insulation layer and into the oxidized silicide layer; and filing the contact hole with a conductive material producing an electrically conductive connection to the noble metal layer.
In accordance with yet an additional feature of the invention, the method includes: after forming the contact hole, removing silicide located at a bottom of the contact hole.
In accordance with yet another feature of the invention, the method includes: fabricating a semiconductor memory having a plurality of storage capacitors, each one of the plurality of storage capacitors having two electrodes and a capacitor dielectric lying between the two electrodes, at least one of the two electrodes being formed by the noble metal la
Gabric Zvonimir
Pamler Werner
Weinrich Volker
Greenberg Laurence A.
Infineon - Technologies AG
Lebentritt Michael S.
Mayback Gregory L.
Stemer Werner H.
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