Method for fabricating a capacitor in a dynamic random access me

Details Method for fabricating a capacitor in a dynamic random access me Method for fabricating a capacitor in a dynamic random access me

1998-10-28

2000-09-19

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438254, 438397, H01L 2120

Patent

active

061211087

ABSTRACT:
A method for forming a cylinder capacitor on a dynamic random access memory (DRAM) device is provided. The method includes sequentially forming a dielectric layer, an etching stop layer, and an insulating layer over a substrate, having a field effect transistor (FET). An opening is formed to expose a source region of the FET by patterning the dielectric layer, the etching stop layer, and the insulating layer. A conductive layer is formed on the insulating layer with the opening being filled. A concave oxide structure is formed on the conductive layer. A portion of the conductive layer other than the concave structure is removed. The concave structure is etched to form two oxide pillars on the conductive layer. Four conductive spacers are formed on each side of the oxide pillars with an electrical coupling with the conductive layer. The oxide pillar and the insulating layer are removed to expose the conductive spacers and a portion of the conductive layer. The conductive layer and the conductive spacers serve together as an lower electrode. A dielectric film is formed over the exposed surface of the lower electrode. An upper electrode is formed on the dielectric film.

REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5399518 (1995-03-01), Sim et al.
patent: 5438013 (1995-08-01), Kim et al.
patent: 5443993 (1995-08-01), Park et al.
patent: 5491103 (1996-02-01), Ahn et al.

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