Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2011-01-04
2011-01-04
Loke, Steven (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000, C438S298000, C257SE21010
Reexamination Certificate
active
07863149
ABSTRACT:
In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).
REFERENCES:
patent: 4236168 (1980-11-01), Herbst
patent: 4905065 (1990-02-01), Selcuk et al.
patent: 5478768 (1995-12-01), Iwasa
patent: 5998251 (1999-12-01), Wu et al.
patent: 6211008 (2001-04-01), Yu et al.
patent: 6403444 (2002-06-01), Fukuzumi et al.
patent: 6448622 (2002-09-01), Franke et al.
patent: 6667209 (2003-12-01), Won et al.
patent: 2001/0005631 (2001-06-01), Kim et al.
patent: 2003/0017669 (2003-01-01), Kiyotoshi et al.
patent: 2003/0136996 (2003-07-01), Park
patent: 2004/0108536 (2004-06-01), Lee et al.
patent: 2004/0150030 (2004-08-01), Nishimura et al.
patent: 2004/0164335 (2004-08-01), DeBoer et al.
patent: 2005/0023640 (2005-02-01), Choi et al.
patent: 2006/0046419 (2006-03-01), Sandhu et al.
patent: 2006/0131632 (2006-06-01), Chae
patent: 2007/0117335 (2007-05-01), Sandhu et al.
patent: 2007/0241428 (2007-10-01), Greenberg et al.
Oehrlein, G. S., et al., “Selective Dry Etching of Germanium with Respect to Silicon and Vice Versa,” J. Electrochem. Soc., May 1991, vol. 138, No. 5, pp. 1443-1452.
Oehrlein, G. S., et al., “Interactive Effects in the Reactive Ion Etching of SiGe Alloys,” Appl. Phys. Lett., May 20, 1991, vol. 58, No. 20, pp. 2252-2254.
Guo, L., et al., “Reactive Ion Etching of Si1-xGexAlloy with Hydrogen Bromide,” Journal of Crystal Growth, 2001, 227-228, pp. 801-804.
Oh, J-H, et al., “Study of the Robust Stack Cell Capacitor Structure Using Double Mold Oxide (DMO) Technology for a Gigabit-Density DRAM and Beyond,” Journal of the Korean Physical Society, Dec. 2002, vol. 41, No. 6, pp. 884-887.
Chen, J., et al., “Formation of Polycrystalline Silicon Germanium/HfO2Gate Stack Structure Using Inductively Coupled Plasma Etching,” J. Vac. Sci. Technol., Jul./Aug. 2003, vol. 21, No. 4, pp. 1210-1217.
Park, J.M., et al., “Novel Robust Cell Capacitor (Leaning Exterminated Ring Type Insulator) and New Storage Node Contact (Top Spacer Contact) for 70nm DRAM Technology and Beyond,” Symposium on VLSI Technology Digest of Technical Papers, Sep. 2004, pp. 34-35.
Kundalgurki Srivatsa
Manger Dirk
Moll Peter
Schloesser Till
Schupke Kristin
Goodwin David
Loke Steven
Qimonda AG
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