Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-08-26
2004-02-03
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C436S169000, C436S169000
Reexamination Certificate
active
06686251
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for fabricating a bipolar transistor having self-aligned base and emitter. The present invention also relates to such a semiconductor device.
(b) Description of the Related Art
Semiconductor deices including therein bipolar transistors have been developed to achieve higher-speed and higher-performance operation. This development is attempted by using finer patterning techniques, wherein the parasitic capacitance and the base resistance of the bipolar transistor are reduced while reducing the junction depth thereof to thereby reduce the transit time of the carriers. One of such patterning techniques is a self-alignment fabrication technique for a bipolar transistor, wherein the emitter region and the base region are separated in a self-alignment scheme, and impurities are introduced from the base lead electrode formed in the periphery of the bipolar transistor to form an external base (or graft base) on the outer periphery of the base region.
In a bipolar transistor having such a self-alignment structure, it is important to reduce the effective emitter width for obtaining excellent high-frequency characteristics such as a steep cut-off frequency (fT) and a high oscillation frequency (fmax). In addition, it is also important not to form a void in a polysilicon layer connected to the emitter region and in the emitter lead electrode connected to the polysilicon layer, thereby obtaining high reliability and a lower emitter resistance of the bipolar transistor.
For example, in order to obtain an excellent oscillation property for a self-aligned bipolar transistor used in a LC oscillator, a higher breakdown voltage (BVebo) should be achieved therein because forward bias and reverse bias are alternately applied in the emitter-base junction. In addition, low-frequency noise should be removed in the self-aligned bipolar transistor if it is used in a voltage controlled oscillator.
FIGS. 14
to
18
consecutively show steps of a conventional fabrication process for a semiconductor device having a self-aligned bipolar transistor. As shown in
FIG. 14
, the process begins with a silicon substrate
101
on which a first silicon oxide film
102
is formed by a thermal oxidation technique, followed by selectively etching a portion of the first silicon oxide film
102
on the emitter region (region for forming the emitter) and the intrinsic base region (region for forming the intrinsic base
108
) by using a photolithographic technique. Subsequently, a first polysilicon layer
103
is deposited on the first silicon oxide film
102
by using a CVD technique, followed by implanting boron ions into the first polysilicon layer
103
by using an ion-implantation technique.
Thereafter, the first polysilicon layer
103
is selectively etched using a photolithographic technique, followed by deposition of a first silicon nitride film
104
by using a CVD technique on both the first polysilicon layer
103
and the first silicon oxide film
102
exposed from the etched first polysilicon layer
103
. Subsequently, the first polysilicon layer
103
and the first silicon nitride film
104
are selectively etched to form an opening
105
which exposes the base region other than a graft base region.
Subsequently, a second silicon oxide film
106
is formed using a thermal oxidation technique on the wall and the bottom of the opening
105
, the second silicon oxide film
106
serving as a diffusion assist layer. Thereafter, boron ions are implanted through the bottom of the second silicon oxide film
106
into the silicon substrate
101
by using an ion-implantation technique, thereby forming an intrinsic base
108
. A second silicon nitride film
107
is then deposited in the opening
105
by using a CVD technique, followed by depositing a second polysilicon layer
110
on the first silicon nitride film
104
in the opening
105
, as shown in FIG.
14
.
Subsequently, as shown in
FIG. 15
, the second polysilicon layer
110
is selectively removed by an anisotropic dry etching technique, to leave a first side-wall polysilicon layer
110
a
on the second silicon nitride film
107
in the opening
105
. The anisotropic dry etching is conducted using reactive ions under the gas ambient wherein the etch rate for the polysilicon layer is larger compared to the etch rate for the silicon nitride film. The gas ambient is such that Cl
2
, HBr and He are introduced at flow rates of 5 to 50 sccm (standard cubic centimeters), 10 to 100 sccm and 1 to 10 sccm, respectively, for example.
During the anisotropic dry etching step, the ions reflected by the first side-wall polysilicon layer
110
a
in the opening
105
are concentrated on the bottom of the inner side of the polysilicon layer
110
a,
thereby increasing the etched amount of the bottom of the opening
105
to form a trench
111
on the bottom. The trench
111
may penetrate the second silicon nitride film
107
to reach the second silicon oxide film
106
, as shown in FIG.
15
. Although the thick second silicon nitride film
107
reduces the aspect ratio of the opening
105
for preventing occurrence of voids in the polysilicon layer etc, in the opening
105
, sufficient over-etching is not conducted for the thick second silicon nitride film
107
for avoiding a larger depth for the trench
111
.
Subsequently, as shown in
FIG. 16
, another anisotropic dry etching process is conducted using the first side-wall polysilicon layer
110
a
as a mask to remove a portion of the second silicon nitride film
107
on the emitter region. The gas ambient in the another anisotropic dry etching is such that the etch rate for the silicon nitride film is larger than the etch rate for the silicon oxide film. For example, SF
6
and He are introduced during the another anisotropic dry etching at flow rates of 40 to 200 sccm and 50 to 250 sccm, respectively, while using reactive ions. The another dry etching increases the depth of the trench
111
to form a deep trench
111
a,
which penetrates the second silicon oxide film
106
to reach the intrinsic base
108
.
Subsequently, wet etching is conducted using a mixture of HF, HNO
3
and CH
3
COOH to remove the first side-wall polysilicon layer
110
a
within the opening
105
, further increasing the depth of the trench
111
a
which has already reached the intrinsic base
108
.
Subsequently, as shown in
FIG. 17
, a portion of the second silicon oxide film
106
on the emitter region is removed by wet etching using a hydrofluoric acid based liquid. Thereafter, the native oxide film on the intrinsic base region is removed by using a hydrofluoric acid based liquid, followed by depositing a second polysilicon layer
113
while introducing SiH
4
gas into the deposition chamber. Arsenic ions are then introduced into the second polysilicon layer
113
by using an ion-implantation technique.
Subsequently, an emitter injection treatment is conducted wherein an emitter
114
is formed by diffusing the arsenic ions in the third polysilicon layer
113
toward the intrinsic base
108
by solid phase diffusion. In this emitter injection treatment, although the trench
111
a
filled with the third polysilicon layer
113
does not penetrate the intrinsic base
108
, there is some possibility depending on the process conditions that the diffused ions allow the trench
111
a
to electrically penetrate the intrinsic base
108
while diffusing toward the silicon substrate
101
which constitutes the collector. Thereafter, a portion of the second polysilicon layer
113
is selectively removed.
Subsequently, as shown in
FIG. 18
, a first interlayer dielectric film
115
is formed on the first silicon nitride film
104
and the second polysilicon layer
113
, followed by selectively etching thereof on the second polysilicon layer
113
and forming consecutively an emitter barrier metal layer
119
having a hollow cylindrical shape and an emitter lead electrode
120
having a solid cylindrical shape.
Further, an emitter electrode
121
having a planar size l
NEC Compound Semiconductor Devices Ltd.
Pham Long
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