Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-02
2002-09-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06453444
ABSTRACT:
BACKGROUND OF INVENTION
The present invention relates to modeling of integrated circuits, and, more particularly, to the extraction of inductances of the interconnections of integrated circuits for the purpose of simulating such circuits.
In the design of integrated circuits, simulation of circuit function and performance has become an indispensable part of the design process. Simulation is carried out using a computer and simulation software that accepts models of the devices and interconnections of the circuit being simulated. It is obvious that the reliability of the simulation of an integrated circuit depends on the accuracy of the models that are used by the simulation software.
With the design of more densely packed VLSI circuits, the interconnection lines of such circuits have smaller cross sections and are packed closer together. As a result, RC delays of the interconnect wires have become an important limitation on circuit performance, and capacitive coupling between interconnect wires has become a significant source of on-chip noise. In addition, increasing chip densities and switching speeds have imposed a much heavier burden on the power and ground distribution lines to supply sufficient current to switching circuits, and the &Dgr;I noise caused by heavy transient current demands of switching circuits is becoming a more serious problem.
In an effort to overcome these problems, next generation technologies can be expected to make increasing use of low-resistivity metals, such a copper, and low dielectric constant insulators. Chip designers routinely make power and ground distribution lines using wide, thick upper-level metal and make long signal lines in the same way to reduce resistance. While these improvements reduce RC delays of signal lines and reduce &Dgr;I noise on power and ground lines, it has now become important to take into account the inductance and inductive coupling of signal lines in simulating the performance of an integrated circuit.
Inductance and inductive coupling have become important in timing and noise analysis of signal lines in several ways. Firstly, inductance must be included in the model of the circuit to accurately predict rise and fall times, as well as delays in timing analysis. Secondly, overdriving an inductive interconnect line can result in an under damped ringing response. Thirdly, inductive coupling, along with capacitive coupling, can be a significant source of noise on a “quiet” signal line that runs close to another signal line carrying a signal having high frequency components.
Printed circuit board (PCB) and package designers have long been concerned about signal line inductances and return paths for currents in such inductances and typically provide discrete ground and power supply planes to control signal line impedance. Because inductance has not been of concern until recently for on-chip wires in digital VLSI circuits, designers have largely viewed such on-chip signal wires as single-ended distributed RC lines without concern for current returns. Power and ground distribution lines have been designed independently to satisfy power and ground requirements of switching circuits and to minimize the &Dgr;I noise. When inductance is taken into account in modeling high frequency integrated circuits, the layout of the power and ground distribution lines has an important effect on the response of inductive signal lines in the circuit.
The conventional approach to designing the layout of power and ground distribution lines in a VLSI integrated circuit chip is to create an on-chip grid. Referring to
FIG. 1A
, there is shown an illustrative cross section of an integrated circuit chip having five levels of conductors designated by M
1
, M
2
, M
3
, M
4
and LM. The power and the ground distribution network, which is shown in black, have lines extending in a vertical direction (i.e., parallel to one edge of a rectangular chip) in conductor levels M
1
, M
3
and LM, and lines extending in a horizontal direction (i.e., parallel to the orthogonal edge of the rectangular chip) in conductor levels M
2
and M
4
.
Turning to
FIG. 1B
, there is shown an illustrative plan view of the power and ground distribution network in the form of a grid. At high frequencies, the power supply and ground are sufficiently decoupled so that the power distribution lines and the ground distribution lines serve equally well in providing return paths for signal line inductances.
Referring to
FIG. 1C
, there is shown a cross-section view of the design for power and ground distribution used in the Digital Equipment Corporation Alpha 21264 chip, in which two entire metal levels
108
and
109
are dedicated to the distribution of power and ground by providing what amounts to a power plane and a ground plane in a manner conventional to PCB design. Openings are made in these power and ground planes to provide vias for connecting signal lines on opposite sides of the power and ground planes. While the design approach of
FIG. 1C
provides more control and predictability in signal line, and power and ground line inductances, it is generally considered inefficient usage of the chip metallization levels because wiring resources are always scarce in VLSI circuit chips. Therefore, the grid layout for power and ground distribution, which does not provide well defined return paths for signal line inductances, is the one that is commonly used in high frequency VLSI circuit chips.
To allow equivalent circuits to be developed in complex integrated circuits in which return paths for signal line inductances are not known, the calculation of partial inductances is traditionally used. The partial inductance technique, which assigns portions of a loop inductance to segments along the loop, is described in E. B. Rosa, “The Self and Mutual Inductance of Linear Conductors,” Bulletin of the National Bureau of Standards, 4, pp. 301-344, 1908. A book by F. Grover, entitled “Inductance Calculations: Working Formulas and Tables,” published by Dover, New York, 1962 provides a comprehensive tabulation of formulae for partial inductances and partial mutual inductances for conductors of different geometries. Applying partial inductances to the modeling of complex multi-conductor networks was formalized by Ruehli with the development of partial-element equivalent circuits (PEEC), as described in A. E. Ruehli, “Inductance Calculations in a Complex Integrated Circuit Environment,” IBM Journal of Research and Development, 16(5), pp. 470-481, 1972.
In the partial inductance approach, signal lines, power distribution lines and ground distribution lines are treated equivalently, therefore resulting in a very large, densely-coupled inductance matrix representation of the interconnection network. In the partial inductance matrix representation of circuit inductances, a matrix is derived that has as its main diagonal elements the partial self inductances of all signal lines, power distribution lines and ground distribution lines of a circuit, and has as its off-diagonal elements the partial mutual inductances between each one of the signal lines, power distribution lines and ground distribution lines with every other one of such lines in the circuit. Thus an inductance matrix provides a convenient representation of the inductances of a circuit and the elements of the matrix may be used by a circuit simulation program together with circuit resistance and capacitance to model the performance of the circuit. However, the complete inductance matrix of a VLSI circuit derived using the partial inductance technique is so large as to be impractical for use in the simulation of the circuit. Moreover, such a large inductance matrix representing every wire coupled to every other wire in the circuit is not necessary to provide sufficiently accurate circuit simulations.
One approach to make the inductance matrix sparse is to truncate the matrix by discarding those terms that are below a certain threshold. However, truncation does not guarantee that the resulting truncated inductance matrix will be positive semi
Baker & Botts L.L.P.
Do Thuan
Smith Matthew
The Trustees of Columbia University in the City of New York
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