Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-20
2001-09-18
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090
Reexamination Certificate
active
06292393
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89104361, filed Mar. 10, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for extracting substrate coefficient of a flash memory preferably by a gate induced drain leakage (GIDL) manner so as to reduce the measuring time and prevent measurement errors from occurring.
2. Description of Related Art
A flash memory as well known has better read/write performance than other types of non-volatile memory, such as electrically erasable programmable read only memory (EPROM), or called as EEPROM. Since the flash memory has better performance, it is very suitable for uses in portable computer, cellular phone, or digital camera. Generally, the flash memory is divided into two types that one is NAND type and one is NOR type. The NAND type is characterized by that the memory cells are coupled in cascade by the bit line. The NOR type is characterized by that the memory cells are coupled in parallel by the bit line. As well known, the NOR-type flash memory has faster speed to access data so that the NOR-type flash memory has wider applications than the NAND-type flash memory in a memory system operated at a higher frequency.
Usually, in the operations of flash EPROM, EPROM, and EEPROM, the floating gate potential is the key parameter for the operations. The floating gate potential is set by capacitance coupling from different terminals and the stored charge density in the floating gate. The complete coupling parameters of a memory cell include control gate coupling coefficient &agr;cg, drain coupling coefficient &agr;d, source coupling coefficient &agr;s, and substrate coupling coefficient ab. Currently, many experimental methods have been proposed for extracting the ratios of the drain coupling coefficient &agr;d to the gate coupling coefficient &agr;cg, that is, &agr;d/&agr;cg, and the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg. However, those conventional methods cannot directly extract the substrate coupling coefficient &agr;b.
One of the conventional method (“A new technique for determining the capacitive coupling coefficients in Flash EPROMs” EDL 13, No. 6, June 1992, pp. 328-331”) to obtain the coupling coefficients of a flash memory cell includes:
A. a flower Nordheim (FN) erase saturation manner is used to obtain a relation of &agr;cg/(1−&agr;s)=&Dgr;Vs/&Dgr;(&Dgr;Vt);
B. a gate induced drain leakage (GIDL) manner is used to obtain &agr;cg/&agr;s and &agr;cg/&agr;d;
C. A normalizing rule requires &agr;d+&agr;s+&agr;b+&agr;cg=1.
According to the equations of A, B, and C above, the coupling coefficients of &agr;d, &agr;s, &agr;b, and &agr;cg are solved, in which one of the four coefficients is still unknown due to only three linear equations being set.
This conventional method has disadvantages as follows:
1. It is hard to know which region is the actual saturation region of the threshold voltage Vt.
2. It is very time consuming.
3. It includes the FN erase saturation manner and the GIDL manner. Another conventional method is so-called a subthreshold method (“Analysis of the subthreshold slop and the linear transconductance techniques for the extraction of the capacitance coupling coefficients of Floating-gate devices”, EDL 13, No. 11 November 1992, pp. 566-568).
Also, another conventional methods (R. Bez et al., IEDM90, pp. 90-101) are following:
A. a force constant Id method is used but this method is easy to disturb the memory cell, causing measurement errors.
B. d(&Dgr;Vt)/dt deviating from its exponential trend at Vfg=Vd, where Vfg is the voltage level at the floating gate and Vd is the voltage level at the drain region, but this method is hard to obtain the extracted position of the trend turning point, and is also time consuming.
SUMMARY OF THE INVENTION
As embodied and broadly described herein, the invention provides a method for fully extracting coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method of the invention includes keeping the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient &agr;d to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg. Similarly, keeping the drain voltage Vd and the source voltage Vs fixed and varying the control gate voltage Vcg and the substrate voltage Vb, a third coefficient ratio of the substrate coupling coefficient &agr;b to the gate coupling coefficient &agr;cg, that is, &agr;b/&agr;cg. The first coefficient ratio &agr;d/&agr;cg, the second coefficient ratio &agr;s/&agr;cg, and the third coefficient ratio &agr;b/&agr;cg incorporate a normalization equation of &agr;d+&agr;s+&agr;b+&agr;cg=1, so that all four coefficients &agr;d, &agr;s, &agr;b, and &agr;cg can be exactly solved.
Since the method of the invention uses only the GIDL manner to extract all coupling coefficients without ambiguity, the Vt saturation region can be exactly figured out. Moreover, since only the GIDL manner is used, the measure time is effectively reduced, and the measurement error is effectively prevented from occurring.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4977537 (1990-12-01), Dias et al.
Chao Chuan-Jane
Huang Chih-Mu
Kao Chi-Hung
Tsai Jung-Yu
Fears Terrell W.
Huang Jiawei
J. C. Patents
Winbond Electronics Corp.
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