Method for extending the local memory address space of a...

Details Method for extending the local memory address space of a... Method for extending the local memory address space of a...

2007-02-06

2007-02-06

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S154000, C711S205000

Reexamination Certificate

active

10040920

ABSTRACT:
A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.

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Kondo, et al., “SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing”,IEEE Comput. Soc., Computer Design 2000, Proceedings 2000 International Conference on Austin, TX, pp. 105-111, Sep. 17, 2000.

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