Method for evaluation of scalable symmetric multiple...

Details Method for evaluation of scalable symmetric multiple... Method for evaluation of scalable symmetric multiple...

2005-04-19

2005-04-19

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S171000, C711S119000, C711S172000, C703S028000

Reexamination Certificate

active

06883071

ABSTRACT:
A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

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Melnyk, et al., “Scalable Parametrizable SMP System Core Architecture”, © Feb. 20012CADSM, p. 90-91.

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