Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-11-19
2004-06-01
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000, C711S154000, C711S219000, C709S217000
Reexamination Certificate
active
06745299
ABSTRACT:
TECHNICAL FIELD
The technical field relates to multiple processor computer system designs. More particularly, the technical field relates to systems and methods of evaluating scalable symmetric multiple processor cache coherency protocols and algorithms.
BACKGROUND
Managing memory and memory cache units is a critical aspect of the design, development and testing of multiple processor computer systems, particularly with the growing number of processors and system buses implemented in existing and planned scalable symmetric multiple processor systems. The coherency of cache memories utilized by each of the processors and the system as a whole is a critical performance and accuracy issue.
Several approaches have been taken in the prior art in attempting to evaluate cache coherency. Two of the more prominent are formal verification and system-wide simulation based evaluation.
Formal verification involves the creation of mathematical models to represent the cache coherency protocol. Formal verification becomes very complex as the coherency scheme scales up and becomes complex itself. It is in fact quite difficult, if not impossible, to apply formal verification to modern, highly scaled and complex symmetric multiprocessing systems. Additionally, formal verification can not be applied during production for final product testing and evaluation.
System-wide simulation based evaluation requires detailed cycle by cycle timing of events across an entire system. Coherency schemes often involve complicated rules which govern the ownership of a given global cache line. Adding to the complexity is the phased nature of modem processor buses. It becomes very tricky to track the phase of every transaction on every bus in the entire symmetric multiprocessing system. Systems can have 10 or more buses and 16 or more processors with outstanding transactions. The intrinsic complexity of this approach prohibits its use during production or final product testing and evaluation as in the formal verification approach.
What is needed is a computationally efficient method and system for implementing and evaluating scalable symmetric multiple processor cache coherency protocols and algorithms.
SUMMARY
In one respect, what is described is a system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms. The system includes a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system includes a central electronics complex (CEC), one or more first buses connected to the CEC, one or more first processor slots connected to the one or more first buses, and a memory. The system also includes an application specific integrated circuit (ASIC) replacing the processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system; a first memory cache unit associated with each ASIC; one or more second buses connected to each ASIC; one or more second processors connected to each second bus; and a second memory cache unit associated with each second processor. The memory, the first memory cache unit, and the second memory cache unit each comprise one or more multiple-byte cache lines wherein one byte of each the multiple-byte cache lines is reserved for access by one of the one or more second processors.
In another respect, what is described is a method for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms. The method includes the steps of setting up an initial state of a scalable symmetric multiple processor computer system, initializing all data structures of the scalable symmetric multiple processor computer system beyond the initial state, tracking write and read transactions issued to memory cache lines, and comparing a listing of the initial state against a listing of a state resulting from the write and read transactions. The method includes further steps to ensure each second processor writes and reads to and from the specific byte address in the cache line assigned to that second processor, and that data read in a read transaction from a specific byte address corresponds to any data previously written to that same byte address.
In yet another respect, what is described is a computer-readable medium on which is embedded a program. The embedded program includes instructions for executing the above method.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of an embodiment with reference to the below-listed drawings.
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Bushey Robert D.
Larson Kelly
Hewlett--Packard Development Company, L.P.
Peugh Brian R.
Sparks Donald
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