Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
2003-05-21
2004-08-17
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S312000, C716S030000
Reexamination Certificate
active
06777147
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates to photolithographic processing methods and more particularly to calculating process effects of multiple exposure techniques therefor.
Typically, a device such as a MOSFET chip is formed on a semiconductor wafer by formation of several layers of material. Most of those layers formed are manufactured using photographic patterning techniques, e.g. photolithography, to expose a target on the device to form a pattern in a photosensitive medium. During the manufacturing process, a pattern for each of the layers on the device is printed with a single exposure of a photosensitive medium (photoresist layer) on the target to form a photolithographic mask as a result of the exposure of the photosensitive layer (photoresist layer) followed by development thereof.
It is well known how to calculate or predict effects of process errors from a single exposure technique for the exposure of photosensitive layer, e.g. photoresist for that purpose. The calculation in a simulation of such effects is commonly known as the process latitude or process window for a process such as a lithographic process which is expressed by the equation described next.
Process Window Expression for a Single Exposure System
The simulated Process Window PW for a single exposure system is defined by the equation as follows:
PW=AE□
pw
(FEM,E,F)
Where the parameters are:
FEM=linewidth vs. focus and dose curves,
E=the exposure dose variation associated with FEM analysis,
F=Focus variation associated with FEM, and
f
pw
=the commonly known process window.
Process window refers to the range of lithographic process conditions (e.g. defocus and exposure dose) within which critical mask pattern features will have printed dimensions that are within a desired tolerance range.
A problem arises when more than one exposure technique is being explored as a viable option for printing critical lithographic levels.
For example, one technique that can require a double exposure is the implementation of the Alternating Phase-Shift Mask (altPSM) method, wherein as a first step an altPSM mask, such as the exemplary altPSM mask
8
shown in
FIG. 1A
is used by passing radiation therethrough to expose a target on a photosensitive layer. Then follows the second step of exposing the target with radiation passed through a Trim mask such as the exemplary Trim mask
9
shown in FIG.
1
B. The Trim mask exposure is employed to trim out and/or remove unwanted features of the photosensitive layer (photoresist or resist), leaving only the desired patterns in the photosensitive layer (photoresist) on the device (chip/wafer) to form the final desired image.
The exemplary altPSM mask
8
shown in
FIG. 1A
, which is 1000 nm wide, has an opaque narrow margin LL on the left and a mirror image opaque narrow margin RR on the right. In
FIG. 1A
, the margins LL/RR, which manifestly block the passage of radiation therethrough, are 50 nm wide. There is a central opaque divider D
1
midway between the narrow margins LL/RR which is 100 nm wide, which also manifestly blocks the passage of radiation therethrough. On the right and left of the central opaque divider D
1
, between the margins LL/RR are left/right portions L
1
/R
1
of the altPSM mask each of which is 400 nm wide. The right portion R
1
of the altPSM mask passes radiation therethrough with a phase shift of zero degrees (0 °). The left portion L
1
of the altPSM mask passes radiation therethrough with a phase shift of Ï□(180 °). A first exposure is created from the altPSM mask of FIG.
1
A.
The exemplary Trim Mask
9
shown in
FIG. 1B
, which is also 1000 nm wide, has no opaque margins. In this case there is a wider central opaque divider D
2
midway between the edges, if the Trim mask
9
is 150 nm wide. On the right and left of the central opaque divider D
2
, between the edges of the trim mask
9
are left/right portions L
2
/R
2
of the Trim mask
9
, each of which is 425 nm wide.
By providing a second exposure of the photoresist on the target device through the Trim mask
9
of
FIG. 1B
, the effect of the first exposure on the target device is affected (modified). While it is well known how to calculate or predict the effects of process errors with single exposure techniques, it is difficult to calculate or predict the composite effects of process errors in double exposure schemes, as the second exposure parameters are largely independent from the first.
Several patents which have dealt with multiple exposure techniques but which differ substantially from the present invention are described below.
U.S. Pat. No. 5,527,645 of Pati et al. for ‘Systematic Method for Production of Phase-Shifting Photolithographic Masks” describes a method of producing a photolithographic mask with a transmission function in which light is transmitted through non-opaque portions of a mask positioned in an object plane and in which an image is formed on an image plane. Definition of a binary image pattern to be formed by the illumination system on the image plane is followed by generating a continuous mask function of continuously-varying phase which satisfies predetermined error criteria based on the transmission function and the binary image pattern. Then the mask function is transformed into a quadrature-phase mask function by dividing the continuously-varying phase into four phase levels. Next, the Pati patent generates a mask in accordance with the quadrature- phase mask function, wherein the mask includes a plurality of pixel regions each of which has a transmittance corresponding to one of the four phase levels. The Pati patent describes a method of fabricating an altPSM mask, but it does not describe a way of analyzing or predicting the final printed patters on a wafer.
U.S. Pat. No. 5,807,649 Liebmann et al. for “Lithographic Patterning Method and Mask Set Therefor with Light Field Trim Mask” which is commonly assigned describes a lithographic patterning method and mask set using a phase shift trim mask having mask dimensions increased in block size so as to remove previous exposure defects. There is no discussion of the process effects on the final critical resist pattern on a wafer.
U.S. Pat. No. 5,532,090 Borodovsky for ‘Method and Apparatus for Enhanced Contact and Via Lithography” describes a method and apparatus for forming openings in a photosensitive layer. An unpatterned photosensitive layer is exposed to a first mask having an opening pattern with dimensions within tight process tolerances. Before development, the photosensitive layer is exposed to a second mask with a grid of clear spaces around the opening pattern. The combined exposure through the two masks forms a latent image with a smaller opening. Using two exposures, with the exposure dose for each designed to control the intensity profile, a reduced dimension opening is formed. The Borodovsky patent describes a technique for forming small holes in resist, but does not relate to methods of calculation/quantifying of process effects upon final resist patterns.
U.S. Pat. No. 5,635,316 of Dao for ‘Layout Methodology, Mask Set, and Patterning Method for Phase-shifting Lithography” describes a device layer layout method for patterning a photosensitive layer. Device features are placed on lines running in rows and/or columns during layout. The lines and/or columns are extracted from the database to produce a layout of the phase-edge phase shifting layer. The photosensitive layer may be exposed to a mask that corresponds to that layout, producing a latent image of the rows and/or lines. The photosensitive layer is also exposed to the device layer layout to expose unwanted portions of the phase-edge layer. Dao et al. describes an application for multiple exposures which does not relate to a method of calculating process effects.
U.S. Pat. No. 6,159,644 of Satoh et al. for ‘Method of Fabricating Semiconductor Circuit Devices Utilizing Multiple Exposures” describes a method of making such devices which enhances an alignment at the time of making the device
Bukofsky Scott J.
Fonseca Carlos A.
Lai Kafai
C. Li Todd M.
Young Christopher G.
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