Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10794756
ABSTRACT:
Broadly speaking, a method is provided for evaluating nets in a crosstalk noise analysis. More specifically, a method is provided for evaluating timing window overlap between a pair of nets. The method includes selecting one timing window from each net of the pair of nets for analysis. The method further includes analyzing characteristics of the timing windows selected from the pair of nets to identify a timing window overlap presence, wherein the timing window overlap presence can exist between any two timing windows associated with each net of the pair of nets, respectively.
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Amatangelo Matthew J.
Hojat Shervin
Mains Robert E.
Sutherland Jeannette N.
Martine & Penilla & Gencarella LLP
Siek Vuthe
Sun Microsystems Inc.
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