Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-29
2003-09-09
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06618844
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI).
BACKGROUND
As physical circuit densities on Very Large Scale Integrated (VLSI) chips increase and the performance (clock frequencies) increases, the signal integrity of on chip electrical nets becomes a major design consideration. The signal integrity of the on chip nets is a function of the electrical noise margin of the receiver circuits and the magnitude of the electrical noise affecting the nets. A source of electrical noise is the transient fluctuations of the local power supply voltages caused by the switching of circuits. The magnitude of this noise is a function of the number of simultaneous switching devices, their sizes, load capacitance, physical positions and densities on the chip, as well as the electrical characteristics of the power supply distribution.
A design technique employed to manage this transient power supply noise is to place decoupling capacitance on the power supply locally to where the sources (switching devices causing the noise) are located. These capacitors dampen the high frequency noise on the power supply distribution. Unfortunately, in typical applications the required amount of decoupling capacitance is unknown or estimated. Thus, if excess capacitance is used, valuable chip area is wasted, if insufficient capacitance is used, generated high frequency noise remains unabated. Therefore, there is a need in the art for a method for evaluating the amount of decoupling capacitance in a given area or within a given area of a noise source and determining if the decoupling capacitance employed is sufficient.
SUMMARY OF THE INVENTION
A method for analyzing decoupling capacitance (dcap) utilization by surrounding and counting components within a predefined proximal area. Included in the method is an analysis of the usage count for each dcap, the distance from the devices, and the x,y locations of the devices and dcaps. Also, taken into account are the orientations and size of the components for each instance usage. The calculations have been performed for a chip with three levels of hierarchy. That is, each chip comprises a multitude of elements termed units. Typically there are ten to twelve units to a chip, but the number may vary depending upon factors such as the size and density of the units employed. Each unit in turn, may include a multitude of macros. In common applications each unit will be comprised of several hundred macros. Again, the number may vary depending upon various factors. Finally each macro is characterized by the actual circuit topology to perform a particular desired function or process. This configuration of the chip is commonly chosen to enable concurrent design of a multitude of macros and units to shorten design and development durations. In a preferred embodiment, the macros employed in the device are under consideration.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the detailed description and to the drawings.
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Becker Wiren D.
Camporese Peter J.
Dansky Allan H.
Eng Kwok Fai
Hoffman Dale E.
Augspurger Lynn
Cantor & Colburn LLP
Garbowski Leigh M.
International Business Machines - Corporation
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