Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-01
2004-11-02
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06813757
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to electrical circuit fabrication, and especially to quality checking circuit mask layouts. The present invention is particularly valuable when employed in connection with manufacturing very large scale integrated (VLSI) circuits.
When fabricating circuits, such as circuits in a semiconductor device, one commonly begins with a database of drawn patterns representing the desired shape of the pattern to be transferred to a substrate to create one portion of the device. The desired pattern is transferred to the device through what is commonly referred to as a photolithographic process. Photoresist material is applied to the substrate, commonly by a spinning-on process. The photoresist material is then patterned using a mask having transparent areas and opaque areas which generally correspond to the shapes of the desired pattern of polygons in the circuit database. The mask is commonly fabricated of a quartz material, and the opaque areas are created on the quartz material using chromium so as to shadow predetermined areas of the photoresist from illuminating light. The substrate and photoresist assembly is exposed to light and then developed using a chemical process. Areas shadowed (i.e., by the chromium areas on the quartz mask) remain after the developing process. Light-exposed portions of the photoresist (i.e., areas beneath transparent quartz areas of the mask) are removed by the developing process.
Some areas of the photoresist material do not conform precisely with the desired pattern in the database. Such incongruities may occur because of light diffraction effects at the mask and other factors of chemical, optical and other natures. Modeling approaches have been employed to seek to predict, identify or correct such a lack of incongruity between the desired database pattern and the pattern transferred to the wafer. Such prior art modeling attempts have met with moderate success. Techniques generally known as proximity correction techniques, including optical proximity correction (OPC) techniques are sometimes employed to modify the pattern to be placed on the mask (i.e., the mask pattern) to one different than that of the database pattern. The modifications are carried out to counteract the distortion effect of the photolithographic process and produce a printed pattern on the substrate more closely matching the desired database pattern. However, it is difficult to determine whether the modified patterns of the mask properly reduce the incongruities between the database pattern and the printed pattern on the substrate. Proximity correction techniques may interfere with presently known prior art approaches used to predict or identify areas of incongruity.
There is a need for a method or technique for evaluating a mask pattern to predict or determine whether the printed pattern produced by the mask is within acceptable limits of incongruity with an associated database pattern, especially when the associated mask pattern employs proximity correction techniques, including optical proximity correction (OPC) techniques.
SUMMARY OF THE INVENTION
A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model includes the steps of: (a) selecting a reference locus; (b) determining a sampling direction from the reference locus; (c) selecting a sampling locus in the sampling direction; (d) evaluating a model factor at the sampling locus; and (e) applying at least one predetermined criterion to the model factor to determine a conclusion. If the conclusion is a first inference, (f) repeating steps (c) through (e). If the conclusion is a second inference, (g) determining whether the evaluation is complete and repeating steps (a) through (g) until the evaluating is complete.
It is, therefore, an object of the present invention to provide a method for evaluating a mask pattern to predict or determine whether the printed pattern to be produced by the mask is within acceptable limits of incongruity with its associated database pattern, especially when the associated mask pattern employs proximity correction techniques, including optical proximity correction (OPC) techniques.
Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings, in which like elements are labeled using like reference numerals in the various figures, illustrating the preferred embodiments of the invention.
REFERENCES:
patent: 5885748 (1999-03-01), Ohnuma
patent: 6081658 (2000-06-01), Rieger et al.
patent: 6492066 (2002-12-01), Capodieci et al.
patent: 6643616 (2003-11-01), Granik et al.
Aton Thomas J.
Chang Mi-Chang
Brady III W. James
Garbowski Leigh M.
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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