Method for etching vias

Details Method for etching vias Method for etching vias

2005-01-25

2005-01-25

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C712S029000, C712S029000, C712S029000, C712S029000

Reexamination Certificate

active

06846747

ABSTRACT:
An improved method for etching a substrate that reduces the formation of pillars is provided by the present invention. In accordance with the method, the residence time of an etch gas utilized in the process is decreased and the power of an inductively coupled plasma source used to dissociate the etch gas is increased. A low bias RF voltage is provided during the etching process. The RF bias voltage is ramped between different bias levels utilized during the etch process. An inductively coupled plasma confinement ring is utilized to force the reactive species generated in the inductively coupled plasma source over the surface of the substrate. These steps reduce or eliminate the formation of pillars during the etching process.

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