Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1995-08-03
1997-08-05
Dang, Trung
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438637, 438704, 438696, H01L 2144
Patent
active
056542380
ABSTRACT:
A method of etching vias without directional etching damage to the substrate. A pattern image is formed on an insulating layer of known thickness over a substrate. A conformal layer is formed on the pattern image. A vertical contact hole through the conformal layer and into the insulating layer is produced by directional etching. The directional etch also leaves conformal sidewall spacers of a defined width. The depth of the vertical contact hole is equal to the thickness of the insulating layer minus the width of the conformal spacer. The insulating layer is then removed by an isotropic wet etch to achieve a near vertical edge contact hole without directional etching damage to the substrate. The sidewall spacers may also be removed by etching prior to removal of the insulating layer.
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Kerbaugh, et al., "Methods of Forming Small Contact Holes", IBM Technical Disclosure Bulletin V30, N8, dtd Jan. 1988, pp. 252-253.
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Cronin John Edward
Potter Michael David
Starkey Gorden Seth
Dang Trung
International Business Machines - Corporation
Walter, Jr. Howard J.
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