Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-11-01
2003-12-02
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S721000, C438S723000, C216S062000
Reexamination Certificate
active
06656847
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the etching of silicon nitride selective to titanium silicide and the formation of multi-level contact openings for quartermicron devices using an oxide etch followed by an in-situ silicon nitride etch selective to titanium silicide.
2) Description of the Prior Art
In semiconductor manufacturing, such as a DRAM device, silicon nitride hard masks are often used to protect gates during subsequent processing. In these same devices, titanium silicide is often used, such as on source and drain regions. Typically, both the silicon nitride hard mask and the titanium silicide have an overlying dielectric layer composed of one or more layers of silicon oxide, BPTEOS, PETEOS, and the like. It is desirable to form contact openings to form interconnections to the gate and titanium silicide. However, to form these contact openings, it is necessary to etch through the dielectric layer and the silicon nitride hard mask without damaging the titanium silicide. As device geometry is scaled down to quartermicron and below, the aspect ratio increases to greater than 8, further complicating the contact opening etch.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following US Patents.
U.S. Pat. No. 4,529,476 (Kawamoto et al.) teaches a CH
2
F
2
—O
2
etch through a BPTEOS/PETEOS oxide and a SiN hard mask.
U.S. Pat. No. 5,728,619 (Tsai) discloses a C
x
H
y
F
z
etch through oxide and stopping on a TiSi
x
layer.
U.S. Pat. No. 5,366,590 (Kadomura) teaches an oxide etch using a high density plasma with high selectivity to Si
3
N
4
.
U.S. Pat. No. 5,468,342 (Nulty et al.) shows an oxide etch using a SiN hard mask using CH
2
F
2
.
U.S. Pat. No. 5,786,276 (Brooks et al.) teaches a C
x
H
y
F
z
—O
2
etch of SiN over SiO
2
.
U.S. Pat. No. 5,258,096 (Sandhu et al.) teaches an etch through for a BPTEOS/PETEOS oxide stopping on a conductive landing pad.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of etching silicon nitride selective to titanium silicide.
It is another object of the present invention to form low resistance, multi-level contact openings on DRAM devices without damaging titanium silicide layers that are exposed during the etching process.
It is another object of the present invention to etch through a silicon nitride hard mask in a contact opening having an aspect ratio greater than 8, using an etch selective to titanium silicide.
It is yet another object of the present invention to perform the etches of the previous objects in-situ.
To accomplish the above objectives, the present invention provides a method for etching silicon nitride selective to titanium silicide and a two step etch for fabricating multi-level contact openings on a quartermicron device. The process begins by providing a substrate (
10
) having thereover a silicon nitride hard mask (
20
) at one level and a titanium silicide layer (
30
) at another level wherein the silicon nitride hard mask (
20
) and the titanium silicide region (
30
) have an oxide layer (
40
) thereover. In the first step, the oxide layer (
40
) is patterned to form a first contact opening (
25
) and a second contact opening (
35
). The first etch step is performed using C
4
F
8
/CO/Ar/O
2
chemistry. The first contact opening (
25
) stops on the silicon nitride hard mask (
20
) and the second contact opening (
35
) stops on the titanium silicide region (
30
). In the second etch step, any remaining oxide and the silicon nitride hard mask (
20
) are etched through in the first contact opening (
25
) using an etch selective to titanium silicide. The etch comprises CH
2
F
2
and O
2
at a ratio of CH
2
F
2
to O
2
of between about 2 and 4. A key feature of the invention is the second etch step ratio of CH
2
F
2
to O
2
which controls the selectivity of nitride to titanium silicide.
The present invention provides considerable improvement over the prior art. A key advantage of the present invention is the second etch step selectivity of silicon nitride to titanium silicide. The inventors have discovered that controlling the O
2
flow rate in a CH
2
F
2
silicon nitride etch, has the unexpected result of etching silicon nitride with high selectively to titanium silicide. This etch selectivity enables them to thoroughly etch through a silicon nitride hard mask (
20
) forming a low resistance first contact opening (
25
) without etching through a titanium silicide region (
30
) in the second contact opening (
35
).
Because the etch selectivity allows the silicon nitride hard mask to be thoroughly etched through, a contact resistance of less than 10 Ohms can be acheived, providing enhanced performance.
REFERENCES:
patent: 4208241 (1980-06-01), Harshbarger et al.
patent: 4529476 (1985-07-01), Kawamoto et al.
patent: 5258096 (1993-11-01), Sandhu et al.
patent: 5366590 (1994-11-01), Kadomura
patent: 5468342 (1995-11-01), Nulty et al.
patent: 5611888 (1997-03-01), Bosch et al.
patent: 5728619 (1998-03-01), Tsai et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 5786276 (1998-07-01), Brooks et al.
patent: 6087264 (2000-07-01), Shin et al.
patent: 6139702 (2000-10-01), Yang et al.
patent: 10125623 (1998-05-01), None
Sugawara, Manufacture of Semiconductor Device, (English Abstract of JP 10125623 A), May 15, 1998, 2 pages.
Lin Huan Just
Tsai Chia-Shiung
Ackerman Stephen B.
Norton Nadine G.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Umez-Eronini Lynette T.
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