Method for etching integrated-circuit layers to a fixed depth an

Details Method for etching integrated-circuit layers to a fixed depth an Method for etching integrated-circuit layers to a fixed depth an

1991-11-15

1994-07-19

Dang, Thi

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156652, 156653, 156655, 156657, 1566611, B05D 500

Patent

active

053306171

ABSTRACT:
The invention relates to a method for etching an integrated-circuit layer to a fixed depth. The method consists in depositing onto the layer to be etched a protective layer forming a stop layer and then onto the latter a reference layer made of a material compatible with that of the layer to be etched the thickness of the reference layer being proportional to the depth of the etch to be produced. A mask is applied to the reference layer and the etching of this layer is carried out by chemical attack until encountering the stop layer. After removal of the mask and of the stop layer, in the etching zone, the reference layer and the layer of material to be etched 1 are simultaneously subjected to a chemical attack until encountering the stop layer. An etch having the plane dimensions of the etch of the reference layer and a depth proportional to the thickness of the reference layer is thus created. Application to the etching of integrated-circuit layers or to the creation of inverted-T-shaped elements.

REFERENCES:
patent: 4142926 (1979-03-01), Morgan
patent: 4174252 (1979-11-01), Kressel et al.
patent: 4268951 (1991-05-01), Elliott et al.
patent: 4436593 (1984-03-01), Osborne et al.
patent: 4576834 (1986-03-01), Sobczak
patent: 4589952 (1986-05-01), Behringer et al.
patent: 4634495 (1987-01-01), Gobrecht et al.
patent: 4648937 (1987-03-01), Ogura et al.
patent: 4801554 (1989-01-01), Gobrecht et al.
patent: 4832788 (1989-05-01), Nemiroff
patent: 4832789 (1989-05-01), Cochran et al.
patent: 4837180 (1989-06-01), Chao
patent: 5047117 (1991-09-01), Roberts
patent: 5118384 (1992-06-01), Harmon et al.
C. C. Beatty et al., 1987 Proceedings Fourth International IEEE VLSI Multilevel Interconn. Conference, Multilevel Tungsten.
Integrated Circuit Metallization with Chromium Non-Erodible Mask and Etch Stop Layers, Jun. 15-16, 1987, pp. 163-168 (& cvr).

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