Method for etching contact vias in a semiconductor device

Details Method for etching contact vias in a semiconductor device Method for etching contact vias in a semiconductor device

1987-02-05

1988-06-28

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156646, 156653, 156656, 156657, 1566591, 156662, 357 43, 357 59, 357 67, 357 71, 437 31, 437192, 437200, 437228, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

047537094

ABSTRACT:
A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

REFERENCES:
patent: 4107726 (1978-08-01), Schilling
patent: 4436582 (1984-03-01), Saxena
patent: 4466172 (1984-08-01), Batra
patent: 4477310 (1984-10-01), Park et al.
patent: 4507847 (1985-04-01), Sullivan
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4589928 (1986-05-01), Dalton et al.

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